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=l/2*: 25/':,'( + ($'48$57(56 (+ $0,/721 $ 9(18( & $03%(// &$ 7 (/(3+21( ) $; +773 ::: = , /2* &20 z90356 rom and Z90351 otp 64 kword television controller with osd 2yhuylhz the z90356 and Z90351 are the rom and otp versions of a television controller with on-screen display (osd) that contains 64 kwords of program memory and 1k words of ram. ?the Z90351 is the one-time programmable (otp) controller used to develop code and prototypes for specific television applications or initial limited production. program rom and character generation rom (cgrom) in the Z90351 are both programmable. the Z90351 requires zilogs z90369zem emulator with its proprietary zilog developmental studio (zds) software for programing. to view code effects, the emulator uses a zosd board that connects directly to a television screen. refer to figure 1. )ljxuh &rgh'hyhorsphqw(qylurqphqw develop code on pc z90359 Z90351 z90369 in-circuit emulation kit zosd board converts to video display download code to z90359 ice chip program the Z90351 otp review code on tv display
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ?the z90356 incorporates the rom code developed by the customer with the Z90351. customer code is masked into both program rom and cgrom. the z90356 television controller with osd is based on zilogs z89c00 risc processor core. the z89c00 is a second-generation, 16-bit, fractional, twos complement cmos digital signal processor (dsp). most instructions are accomplished in a single clock cycle. this processor features a 24-bit arithmetic logic unit (alu) and a 24-bit accumulator. the processor also contains a six-level stack and three vectored interrupts. 0qvg the z89c00 multiplier is disabled in the z90356 controller. the z90356 contains 64 kwords of program rom and 1 kword of on-chip data ram. program rom space can hold an unlimited number of characters with a 16x16, 16x18, and 16x20 programmable matrix in relocated character generation rom (cgrom), which is only restricted by the available rom. in addition, the z90356 contains four external register banks with eight registers each. additional control registers (ar) are available to control new peripheral blocks like palette banks and memory management. an internal 24-mhz/2 system clock has a phase lock loop (pll) driven by an external 32.768-khz crystal. a six-channel, 4-bit analog to digital converter (adc) supports the following: ? analog front panel control ? audio level input ? vertical blanking interval (vbi) data capture six pulse width modulator (pwm) outputs allow low-cost digital-to-analog conversion (dac). the pwms have 8-bit resolution to control video and audio attributes. a master/slave i 2 c (inter integrated circuit) bus interface provides serial system interconnect to common peripheral functions. twenty-five programmable i/o pins provide flexibility for other digital input/output functions. an ir (infrared) remote capture register facilitates reliable remote data capture. on-chip horizontal synchronization (h sync ) and vertical synchronization (v sync ) circuits generate a video time base (typically used for vcr and set-top applications) in the absence of an available video signal. micro-programmable osd generation logic provides flexibility to tailor osd features and functions. in addition to normal osd functions, closed caption is supported in accordance with fcc report and order on gen docket no. 91-1, dated april 12, 1991. expanded data service (xds) capability is supported as well. the z90356 is packaged in a 52-pin sdip package.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& figure 2 is a block diagram of the internal structure of the chip. figure 3 illustrates the pin locations, and table 1 describes the function of each pin.
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=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 2shudwlrq &38'hvfulswlrqv the z89c00 core is a high-performance dsp that has a modified harvard-type architecture with separate program and data memories. the design has been optimized for processing power and silicon space. the z89c00 used in the z90356 device has been modified. the multiplier is disabled and is not accessible. however, the x and y registers in the multiplier are still available and can be used as general-purpose registers. refer to zilogs z89c00 documentation. 5(6(7 5hvhw , ;7$/ &u\vwdorvfloodwrulqsxw $, ;7$/ &u\vwdorvfloodwrurxwsxw $2 *1' 'ljlwdojurxqg 3rzhu 9&& 'ljlwdo9ff 3rzhu $*1' $qdorjjurxqg 3rzhu 3:0 elw3:0rxwsxw 2 3:0 elw3:0rxwsxw 2 3:0 elw3:0rxwsxw 2 3:0 elw3:0rxwsxw 2 3:0 elw3:0rxwsxw 2 3:0 elw3:0rxwsxw+6<1& ,2 35 3rurxwsxwri5*%pdwul[ ,2 35 3rurxwsxwri5*%pdwul[ ,2 3* 3rurxwsxwri5*%pdwul[ ,2 3* 3rurxwsxwri5*%pdwul[ ,2 3% 3rurxwsxwri5*%pdwul[ ,2 3% 3rurxwsxwri5*%pdwul[ ,2 7deoh =ru=3lq'hvfulswlrq &rqwlqxhg 6\pero 3lq )xqfwlrq 'luhfwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $/8 the 24-bit alu has two input ports, one of which is connected to the output of the 24-bit accumulator. the other input is connected to the 24-bit p-bus; the upper 16 bits are connected to the 16-bit d-bus. ,qvwuxfwlrq7lplqj several instructions are executed in one machine cycle. long immediate instructions and jump or call instructions are executed in two machine cycles. when the program memory is referenced in internal ram indirect mode, it requires three machine cycles. an additional machine cycle is required if the pc is selected as the destination of a data transfer instruction. this only occurs with a register indirect branch instruction. +dugzduh6wdfn a six-level hardware stack is connected to the d-bus to hold subroutine return addresses or data. the call instruction pushes pc+2 onto the stack. the ret instruction returns the contents of the stack to the pc. &385hjlvwhuv the z90356 has 11 physical internal registers and four banks of eight external registers. in addition, it has nine virtual registers. the 11 internal registers are defined in table 2, and the status register is defined in table 3. ,qwhuqdo5hjlvwhuv 7deoh ,qwhuqdo5hjlvwhuv 5hjlvwhu 5hjlvwhu'hilqlwlrq ; ;elwv < <elwv $ $ffxpxodwruelwv 65 6wdwxv5hjlvwhuelwv 3qe 6l[5$0$gguhvv3rlqwhuvelwvhdfk 3& 3urjudp&rxqwhuelwv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& x and y are 16-bit general purpose registers. a is a 24-bit accumulator. the output of the alu is sent to this register. when 16-bit data is transferred into this register, it goes into the 16 msbs and the least significant eight bits are set to zero. only the upper 16 bits are transferred to the destination register when the accumulator is selected as a source register in transfer instruction. sr is the status register that contains the alu status and the control bits listed in table 3. the status register is always read in its entirety. s15-s12 are set/reset by the hardware and can only be read through software. they are set or reset by the alu after an operation. s8-s0 can be written by software. s8, if 0 (reset), allows the hardware to overflow. if s8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. s7 enables interrupts. s6Cs5 are used for short form direct addresses, which are described below. the definitions of s2-s0 are listed in table 4. 7deoh 6wdwxv5hjlvwhu %lw)lhog %lw3rvlwlrq 5: 'hvfulswlrq 1 5 $/81hjdwlyh 29 5 $/82yhuiorz = 5 $/8=hur / 5 &duu\ 5hvhuyhg 5 5hvhuyhg 5hvhuyhg 5 5hvhuyhg 5hvhuyhg 5 5hvhuyhg 23 5: 2yhuiorz3urwhfwlrq ,( 5: ,qwhuuxsw(qdeoh 5hjlvwhu%dqn6hohfwru 5: 5hjlvwhu%dqn 5hjlvwhu%dqn 5hjlvwhu%dqn 5hjlvwhu%dqn 6)' 5: 36kruw)rup'luhfw%lwv 53/ 5: 5$03rlqwhu/rrs6l]h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& pn:b are the pointer registers for accessing data ram. (n= 0, 1, 2 refer to the pointer number) (b = 0, 1 refers to ram bank 0 or 1). they can be read from or written to directly and can point directly to locations in data ram or indirectly to program memory. pc is the program counter. when this register is assigned as a destination register, one nop machine cycle is automatically added to adjust the pipeline timing. ([whuqdo5hjlvwhuv the z90356 module is capable of accessing eight external registers directly using only the three external register address signals that are normally available. two user bits (status register s6-s5) are combined with the register address signals to provide the ability to address four banks of eight registers each. the registers most critical for speed are located together in bank 3. in this specification, all external registers are referred to as: rx(y) where: x is a register number within a register bank; y is a bank number; and z is a bit field number an external register bank can be selected by setting bits 6 and 5 in the status register to define the bank, then specifying the address of the register on the external register address bus. 7deoh 53/'hvfulswlrq 6 6 6 /rrs6l]h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& external registers reside on the chip and are used to control the operation of all the peripheral modules in the device. by reading or writing to the fields in the external registers, the user can interact with the peripheral devices on the chip. 9luwxdo5hjlvwhuv bus is a read-only register that, when accessed, returns the contents of the d-bus. it is a virtual register. (physical ram does not exist on the chip.) dn:b these eight data pointers refer to possible locations in ram that can be used as pointers to locations in program memory. the programmer decides which location to choose two bits from in the status register and which two bits in the operand. this means only the lower 16 possible locations in ram can be specified. at any one time there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in ram. for example, if s3/s4 = 01 in the status register, then d0:0/d1:0/d2:0/d3:0 refers to locations 4/5/6/7 in ram bank 0. 0qvg when the data pointers are being written to, a number is actually being loaded to data ram, so they can be used as a limited method for writing to ram. $gglwlrqdo&rqwuro5hjlvwhuv$5 additional control registers (ar) control new peripheral blocks like palette banks and memory management. to activate ars, r0(1) must be set to 1. ars can be disabled by setting r0(1) = 0, (por) for software backward compatibility or if access to ram location 1ffh is required. the 128 eight-bit control registers (referred as ar or arx) use ram-mapped i/o access. location 1ffh in ram is used to address up to 128 byte-width ars. the ar number and written data are encoded into the data field as illustrated in figure 4. )ljxuh $55hjlvwhu)rupdw when writing to address 1ffh, the data write bit (dwb) and ar number are latched, depending on whether the dwb data field is either written to the selected port (latched) or discarded (not latched). the ar number and corresponding data are read after reading from the previously latched dwb address 1ffh. to write to the ar, the data must be written to address 1ffh; dwb must be set to 1, the port number must be specified in bits 8C14, and actual data must be specified in bits 0C7. 'dwd $5qxpehu ':%
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh ld a, #(%8000 + 29*256 + %57); write 57 (hex) into the ar29 ld %1ff, a; 0qvg the dwb and port number are latched for further reading if necessary. to read from the ar, the address must be previously latched by writing it to address 1ffh with dwb set to 0. bits 0C7 have no meaning. because the bits are not going to be written in this mode, only the port number is latched. ([dpsoh ld a, #%1e00; latch ar30, data is not written ld %1ff, a; ld a, %1ff; read from ar30-%1exx, where xx is current content at least one cycle delay (nop) is required between two consecutive accesses to the ar. if access is performed by a two-cycle instruction, no delay is necessary. external memory must exhibit access times of less than 60 ns. table 5 lists the additional control registers. 7deoh $gglwlrqdo&rqwuro5hjlvwhuv $5 1dph %lw srvlwlrq 'dwd )xqfwlrq 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%% 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%% 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%% 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%% 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%% 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%% 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%%
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 5$0$gguhvvlqj the addresses in ram can be specified in one of three ways. refer to figure 5. 3dohwwhb 76------ --543210 ' '' 5hvhuyhg 3dohwwh&roru255**%% 3dohwwhb 76543210 '' 6dphdv$5iru3dohwwh 3dohwwhb 76543210 '' 6dphdv$5iru3dohwwh 3dohwwhb 76543210 '' 6dphdv$5iru3dohwwh 3dohwwhb 76543210 '' 6dphdv$5iru3dohwwh 3dohwwhb 76543210 '' 6dphdv$5iru3dohwwh 3dohwwhb 76543210 '' 6dphdv$5iru3dohwwh 3dohwwhb 76543210 '' 6dphdv$5iru3dohwwh 5hvhuyhg 3j/rfdwlrq 7------- -6------ --543210 '' 3djhlvorfdwhglqwhuqdoo\325 3djhlvorfdwhgh[whuqdoo\ ,qwhuqdo520lvhqdeohg325 ,qwhuqdo520lvglvdeohgorzsrzhu frqvxpswlrq 3djh2h[whuqdosk\vlfdosdjhqxpehu 3j/rfdwlrq 7------- -6------ --543210 '' 3djhlvorfdwhglqwhuqdoo\325 3djhlvorfdwhgh[whuqdoo\ 5hvhuyhg 3djh2h[whuqdosk\vlfdosdjhqxpehu 3j/rfdwlrq 76543210 '' 6dphdvderyhiru3djh 3j/rfdwlrq 76543210 '' 6dphdvderyhiru3djh 7deoh $gglwlrqdo&rqwuro5hjlvwhuv &rqwlqxhg $5 1dph %lw srvlwlrq 'dwd )xqfwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh 5$0520dqg3rlqwhu$ufklwhfwxuh 0hpru\520dqg5$0 the z90356 has 64k words of read only memory (rom) and 1k words of random access memory (ram). 520 the 64k words mask rom is designed to provide storage for both program memory (progrom) and character set graphic pixel arrays (cgrom). the address boundary between these applications is dependent on the storage required for character graphics. the program rom section can, in theory, be accessed anywhere in the addressable rom space; however, because cgrom usually starts at location 0000h, program rom resides in the higher address locations. the maximum available rom space for program memory depends on the rom reserved for cgrom (for an application) and the rom size of the device selected. 3 3 3 3 3 ; %,7 ; %,7 5$03rlqwhuv )) #3 ' ' ' ' ' ' ' ' 5$0 5$0 'dwd3rlqwhuv ,qwhuqdo520 # ' ##3 66 .[%lw )) 5$03rlqwhuv 3
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& cgrom can be placed anywhere in the 64k rom address space by setting the cgrom address offset register r7(2). this offset is added to the character address before accessing rom. by modifying the cgrom offset, several fonts can be accessed (limited by rom size only). when reset, r7(2) =0 (no offset) for backward compatibility with existing software. refer to figure 6. )ljxuh 5200ds &*520%dqnq&kdudfwhuv 6fdqolqhv q )))& )))' )))( )))) ,qwyhfwru ,qwyhfwru ,qwyhfwru 5hvhwyhfwru 3urjudp520 8swr. &*5202%dqn6fdqolqhv ru%dqnru3urjudp520 &*5202%dqn6fdqolqhv ru%dqnru3urjudp520 . 8swr. 8swr. . 3urjudp520ru&*520
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 5$0 the 1k words ram is organized in four banks of 256 words consisting of 16 bits each. bankl.0 is always accessible. bank0.0 is mapped to other bank(s); only one gauge from 0.x is active through bit selection. see figure 7. )ljxuh 5$0$oorfdwlrq &orfn&lufxlw'hvfulswlrq the processor is able to operate from several clock sources: ? primary phase lock loop vco source (pvco) ? secondary phase lock loop (svco) ? 32.768-khz oscillator clock (osc) in addition, the processor clock can be halted temporarily to select the clock source or access rom without disrupting normal operation of the processor. an external crystal controls the internal 32.768-khz oscillator. the crystal is used as the clock reference for the internal phase locked loop (pll). the pll provides the internal pvco clock for processor operation. sclk is generated internally by dividing the frequency of an appropriate oscillator (pvco) by 2. the frequency of the sclk after por is 12.058 mhz. the sclk signal can be sent to the port16 output pin under software control by setting bit 9 in register r3(1). the svco must be used as the system clock when the osd is generated. the clock switch control register r6(1) defines the source of the sclk for the z90356 core. the block diagram in figure 8 represents the clock switch circuit. bank1.0 bank0.0 256 words 256 words 256 bank0.1 bank0.2 256
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh &orfn6zlwfklqj%orfn'ldjudp ,qsxw'ulyh&lufxlwv the 32-khz oscillator circuit in figure 9 is suggested for proper clock operation. )ljxuh .+]2vfloodwru5hfrpphqghg&lufxlw n+] rvfloodwru 0+] 39&2 0+] 69&2 3// 3// )lowhu 6:,7&+ 6:,7&+ 6:,7&+ 6&/. 'lylghu 5! 5! 5! 69&239&2 1rb6zlwfk )dvw6orz z90356 xtal1 xtal2 68 k w 47 pf 22 pf 10 m w 32.768 khz
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 5hvhw&rqglwlrqv reset conditions including addresses and registers are listed in table 6. 7deoh 5hvhw&rqglwlrqv 5hvhw &rqglwlrq $ggu 5hjlvwhu &rpphqwv 5 uhvhuyhg [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 1rwdydlodeoh 5 &xuvru3dohwwh [ [ [ [ [ [ [ [ [ [ [ [ [ [ &xuvrusdohwwh jdxjh 5 soobiuht [ [ [ [ [ [ [ [ 3//iuhtxhqf\ frqwuro 5 , &blqw [[[[[[[[[[ [, &lqwhuidfh uhjlvwhu 5 sruw [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ elw,2sruw 5 sruw [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ elw,2sruw 5 glu elwsruw gluhfwlrq 5 glu [ [ [ [ [ [ [ elwsruw gluhfwlrq 5 fodpsbsrv [ [ [ [ [ [ [ 3rvlwlrqriylghr fodpssxovh 5 vfonbiuht [ [ [ [ 6wrsvohhsqrupdo prgh 5 elwfqwu [ [ [ [ [ [ [ [ [ 6wrsdqg:'7 elwfrxqwhu 5 vwdqgdugbfwo [ [ [ 2xwsxw+96<1& %olqn&rqwuro 5 $'&bfwo [ [ [ [ $'frqyhuwhu frqwuro 5 fdsbvbfwo [ [ [ [ [ [ [ [ [ [ [ [ [ [ &rxqwhuwlphuv frqwuro 5 forfnbfwo [ [ [ [ [ &orfnfrqwuro vzlwfk9&2'27 5 zgwbvpubfwo [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 605dqg:'7 frqwurolqwhuuxsw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 5 szpbgdwd [ [ [ [ [ [ [ [ elw3:0gdwd 5 szpbgdwd [ [ [ [ [ [ [ [ elw3:0gdwd 5 szpbgdwd [ [ [ [ [ [ [ [ elw3:0gdwd 5 szpbgdwd [ [ [ [ [ [ [ [ elw3:0gdwd 5 szpbgdwd [ [ [ [ [ [ [ [ elw3:0gdwd 5 szpbgdwd [ [ [ [ [ [ [ [ elw3:0gdwd 5 6kdgrz&wuo [ [ [ [ [ [ [ [ 6kdgrzfrorufwuo 5 &*520riivhw &*520riivhw uhjlvwhu 5 klb[bklb[ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ &kdudfwhupxowlsoh fxuuhqwgdwd 5 orb[bplgb[ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ &kdudfwhupxowlsoh qh[wrusuhylrxv gdwd 5 &kb[borb[ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ &kdudfwhupxowlsoh fkdudfwhujudsklfv dwwulexwh 5 dwwubgdwd [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ &kdudfwhudwwulexwh ylghr5$0gdwd 5 rvgbfqwo [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 2qvfuhhqglvsod\ frqwuro 5 fdsbgdwd [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ &dswxuhuhjlvwhu gdwd 5 sdohwwhbfroru 'lvsod\sdohwwh froruxqghuolqh froru 5 rxwsxwsdohwwh 2xwsxwsdohwwh 7deoh 5hvhw&rqglwlrqv &rqwlqxhg
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 3rzhu0dqdjhphqw there are two low-power operating modes for z90356: sleep mode and stop mode. 6/((30rgh in sleep mode, the controller uses the 32.768-khz clock for the sclk to reduce power consumption. 67230rgh in stop mode, the processor is suspended, and the power consumption is minimized. ,23ruw&rqiljxudwlrqv user control can be monitored either through the keypad scanning port or the 16-bit remote control capture register. two input/output port blocks are available for general-purpose digital i/o application. each port bit can be programmed to be either an input or output port. to conserve the device pin count, some port pins are mapped to provide i/o to the adc converter block and i 2 c interface block. the 25 configurable i/o pins are general-purpose pins for functions such as serial data i/o, led control, key scanning, power control and monitoring, and i 2 c serial data communications. port 0 and 1 directions are defined in r6(0) and r7(0), respectively. r4(0) and r5(0) are data registers for both ports 0 and 1 . figure 10, figure 11, and figure 12 indicate i/o configuration and sharing with other functional units.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh %lgluhfwlrqdo3ruw3lqv )ljxuh %lgluhfwlrqdo3lqv0xowlsoh[hgzlwk,&3ruw 9 && 3dg 'luhfwlrq 2,1 2287 2xwsxw ,qsxw w 9 && 3$' 'luhfwlrq ,1 287 ,qsxw w 3257 , & 2xwsxw 2qsxw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh %lgluhfwlrqdo3lqv0xowlsoh[hgzlwk$'&,qsxwv ,qwhuuxswv the z90356 has three external interrupt signals. there are four interrupt sources as follows: ? horizontal sync (h sync ) ? vertical sync (v sync ) ? capture timer ? external event (port09). all interrupts are vectored. the capture timer and port09 are multiplexed to the same interrupt. interrupt priorities are programmable. each interrupt can be masked by setting fields in the external registers. when the z90356 receives an interrupt request from one of the interrupt sources, it executes the interrupt service routine directly for that source. external register r7(1) controls interrupts. 9 && 3$' 'luhfwlrq 2,1 2287 2xwsxw ,qsxw w $qdorj 08;
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7lphuv :dwfk'rj7lphu the watch-dog timer resets the cpu when it times out. external register r7(1) controls the watch-dog timer. 5hdo7lph&orfn a clock timer, in real time, generates ticks every 1000, 250, 62.5 or 15.625 ms. external register r5(1) controls the real time clock. ,5&dswxuh7lphu a capture timer measures time between edges of the ir signal. this timer can be programmed to measure timing from rising-to-rising, falling-to-rising, rising-to-falling, or falling-to-falling edges. the ir capture timer is controlled by external register r5(1). figure 13 is a block diagram of the ir capture register structure. )ljxuh ,5&dswxuh5hjlvwhu%orfn'ldjudp &$3b*olwfk &$3b(gjh *olwfk )lowhu 3uhvfdohu (gjh 'hwhfwru &dswxuh 7lph &dswxuh 5hjlvwhu &dswxuh )odjv < ,5 cap_speed r5(1)<1:0> +dowfdswxuhwlphu 5! &dswxuhggdwd 5 )doolqjhgjhlvfdswxuhg 5hvhw5h! 5dlvlqjhgjhlvfdswxuhg 5hvhw5i! 7lphrxw 5hvhw5f!
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $'& this function employs a 4-bit resolution, flash a-to-d converter. the six-to-one analog input multiplexor and conversion start circuits are controlled by the user program. the 4-bit conversion result is available to be read by the cpu at the end of each conversion. one input channel (adc0) is dedicated for quantizing vbi (vertical blank interval) data for subsequent digital signal processing. another channel, adc5, is typically used for vsync separation from the composite tv signal. these channels (adc0 and adc5) feature a special video clamp circuit that provides dc restoration of the composite video input signal. typical vbi applications include line 21 closed caption, electronic data services, and starsight telecast. the range of adc0 and adc5 is from 1.5 to 2.0 v. the four remaining channels of adc (adc1, adc2, adc3, and adc4) are general pur- pose. they are typically used for tuner automatic frequency control and analog key entry. the range of adc1Cadc4 is from 0 to 5.0 v. the 4-bit adc in the z90356 features six multiplexed inputs. the allowed range of the input signals is different for different adc inputs according to table 7. reference voltages that have been generated internally define the maximum range of the input signal for the adc. nominal values are as follows: ref+ = 2.0 v refC = 1.5 v @ v cc = 5.0 v for other v cc values, the reference voltages must be prorated as follows: ref+ = 0.4 * v cc 7deoh $'&,qsxwv7\slfdo5dqjh ,qsxw 5dqjh9 &odpslqj 7\slfdodssolfdwlrq &9,$'& =520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& refC = 0.3 * v cc the maximum sampling rate of the adc converter is 3 mhz. it takes 4 sclk cycles for valid output data from the adc to become available. this is especially important if the application uses the single-shot mode. the adc exhibits monotonous conversion characteristics with a nonlinearity of less than 0.5 lsb. adc0. the adc has a range of 0.5v (from 1.5v to 2.0v) and is directly multiplexed to the input of the adc. the remaining adc inputs (ranging from 0v to 5v) use agnd and av cc voltage as a reference. figure 14 is a block diagram of the adc inner structure, and figure 15 illustrates adc input circuits. )ljxuh $'&%orfn'ldjudp $'&'dwd3dfnlqj up to four 4-bit adc data samples can be packed into one 16-bit word without software overhead. if r4(1)<9> = 1, every reading of r4(1) returns the result, where the high 12 bits are the three previous adc samples and the low 4 bits are the current one, as illustrated in figure 15. $'& &219(57(5 [ 08; 5() 5() &/$03 &/$03 $'&&&'ghfrghu $'&3 $'&3 $'&3 $'&96<1&ghfrghu = $'&3
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh $'&'dwd3dfnlqj nops between adc accesses are omitted. ld sr,%#20; select regbank1 ld a,ext4 ; turn adc data packing mode on or a, #%0200; ld ext4, a; ld a, ext4; read first adc sample, a = %0005 ld a, ext4; read second adc sample, a = %005e ld a, ext4; read third adc sample, a = %05e7 ld a, ext4; read forth adc sample, a= %5e74 ld a, ext4; read fifth adc sample, first sample is thrown away, a = %e741 the adc is controlled by the external register r4(1). 3xovh:lgwk0rgxodwlrq pulse width modulation is used in conjunction with external low-pass filters to perform digital-to-analog conversion. six pwms (8-bit resolution each) generate signals for the control of video and sound attributes. in case of a chassis employing a frequency synthesis tuner, these pwms can also control video or sound attributes. each pwm circuit features a data register whose contents are set under program control. the data in the register determines the ratio of pwm high to pwm low time. pwm data registers are not initialized when reset. in order to eliminate a potential glitch on a pwm output, it is recommended to initialize pwm data registers before enabling the vcos. external registers r0(2) to r5(2) are data registers for pwm1 to pwm6 accordingly. , &,qwhuidfh there are two hardware modules that support standard i 2 c bus protocol according to the i 2 c bus specification published by phillips in 1992, entitled i 2 c peripherals for microcontrollers data handbook . $'&vdpsoh7 $'&vdpsoh7 $'&vdpsoh7 $'&vdpsoh7
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& the first module, the master, can be configured for fast (400 khz) or slow (100 khz) bit rates and can be used in applications with a single master. the second module, the slave, supports a 7-bit addressing format with both fast and slow bit rates. the z90356 adds two additional nonstandard bit rates (50 khz and 10 khz) and an additional multiplexed master port that is controlled by the i 2 cm_mux control bit. table 8 lists the bit rates for the master i 2 c bus. to suppress possible problems on both data (sda) and clock (scl) lines, digital filters are available for all inputs of the i 2 c bus interface. these filters exhibit a time constant equal to 3t sclk = 250 ns. if the master or slave i 2 c interface is enabled, corresponding i/os (port01 and port02 for the slave, port11 and port12 for the master) must be assigned as outputs. master and slave modules cannot be used simultaneously because of the shared i 2 c data register (see the register r3(0) data field). the software activates i 2 c modules by writing appropriate commands into the control register. to control the i 2 c bus interface, the control register r3(0) toggle bit must point to an appropriate interface (master or slave). m_disable or s_disable bits allow either the master or slave i 2 c interface to be disabled so as not to interfere with any activity associated with the port pins. at power-on reset (por), both i 2 c interfaces are enabled. to use the i 2 c interface, the corresponding port pin (multiplexed with the i 2 c data and clock) must be configured as an output, while m_disable or s_disable bits must be reset to 0 . external register r3(0) controls the i 2 c. table 9 lists the master i 2 c bus interface commands. table 10 lists the slave i 2 c bus interface commands. figure 16 and figure 17 are flow charts of the master and slave modes. 7deoh 0dvwhu, &%xv%lw5dwhv 0rgh , &prgh %lw5dwh $fwxdo%lw5dwh /26orz 2 n+] n+] +,6orz 2 n+] n+] /2)dvw 6orz n+] n+] +,)dvw )dvw n+] n+]
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh 0dvwhu, &%xv,qwhuidfh&rppdqgv &rppdqg 1rwhv)xqfwlrq 7klvfrppdqgvhqgvdvwduwelwiroorzhge\dqdgguhvve\whvshflilhglq wkh3gdwdilhogelwv!wkhqihwfkhvdqdfnqrzohgjphqwlqelw! 7klvfrppdqglqlwldol]hvfrppxqlfdwlrqdqgjhqhudwhv6&/f\fohv 7klvfrppdqgvhqgvrqhe\whrigdwdvshflilhglqwkh3gdwdilhogelwv !wkhqihwfkhvdqdfnqrzohgjphqwlqelw!7klvfrppdqglv xvhglqd:5,7(iudphdqgjhqhudwhv6&/f\fohv 7klvfrppdqgvhqgvelw!dvdqdfnqrzohgjphqw$&. 1$. wkhquhfhlyhvdgdwde\wh7klvfrppdqglvxvhglqd5($'iudph zkhqwkhqh[wgdwde\whlvh[shfwhgdqgjhqhudwhv6&/f\fohv 5hfhlyhggdwddsshduvlqwkh3gdwdilhogelwv! 7klvfrppdqgvhqgvelw!dvdqdfnqrzohgjphqw$&. 1$. 7klvfrppdqglvxvhglqd5($'iudphwrwhuplqdwhgdwdwudqvihu dqgjhqhudwhvrqh6&/f\foh $18//rshudwlrq7klvfrppdqgpxvwehxvhgzlwkd35(6(7elwe! dqgrud372**/(elwf! 8vlqjwkh35(6(7dqgru372**/(elwvzlwkdq\rwkhufrppdqg lqwhuihuhvzlwkwkhorjlfriwkh, &lqwhuidfh 7klvfrppdqguhfhlyhvrqhgdwde\wh,wlvxvhglqd5($'iudphwr uhfhlyhwkhiluvwgdwde\whdiwhuwkhdgguhvve\whlvwudqvplwwhg,w jhqhudwhv6&/f\fohv 7klvfrppdqgvhqgvdvwrselwdqgjhqhudwhvrqh6&/f\foh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh 6odyh, &%xv,qwhuidfh&rppdqgv &rppdqg 1rwhv)xqfwlrq 0 0 0 5hvhuyhg & dqqrwehxvhg 0 0 1 7klvfrppdqgvhqgvelw!dvdqdfnqrzohgjphqw$&. rqo\ wkhquhfhlyhvrqhgdwde\wh7klvfrppdqglvxvhglqd:5,7(iudph dqguhtxluhv6&/f\fohv5hfhlyhggdwdlvuhdgdvd3gdwdilhogelwv ! 0 1 0 7klvfrppdqgvhqgvrqhe\whrigdwdvshflilhglqd3gdwdilhogelwv !wkhqihwfkhvdqdfnqrzohgjphqwlqelw!7klvfrppdqglv xvhglqd5($'iudphdqguhtxluhv6&/f\fohv 0 1 1 5hvhuyhg&dqqrwehxvhg 1 0 0 1 0 1 $18//rshudwlrq7klvfrppdqgpxvwehxvhgzlwkd35(6(7elwe! dqgru372**/(elwf! 8vlqjwkh35(6(7dqgru372**/(elwvzlwkdq\rwkhufrppdqg lqwhuihuhvzlwkwkhorjlfriwkh, &lqwhuidfh 1 1 0 7klvfrpp dqgvhqgvdelw!dvdqrwdfnqrzohgjphqw1$. rqo\ lqd:5,7(ru5($'iudph7klvfrppdqgwhuplqdwhv, & frppxqlfdwlrqdqguhtxluhvrqh6&/f\foh7kh36xoidqlodplghelwd! lvdxwrpdwlfdoo\uhvhwzkhqd3exv\elw!jrhv/rz 7klvfrppdqgvhqgvdelw!dvdqdfnqrzohgjphqw$&. rqo\lq d5($'iudphdqguhtxluhvrqh6&/f\foh7kh6hqggdwdfrppdqg pxvwehh[hfxwhgqh[w7klvfrppdqgdfnqrzohgjhvdqdgguhvv e\whlqd5($'iudph 1 1 1 5hvhuyhg & dqqrwehxvhg
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh 0dvwhu0rgh 67$57 5hdg5! 3%xv\ " \hv qr :ulwh5 ^[[[$ggu5:` qr 3%xv\ :ulwhiudph 5hdgiudph 6hqgdvwduwelwiroorzhg e\delw$gguhvve\wh \hv :ulwh5 ^[[[[[[[[[[[` 3%xv\ " 0ruhe\whv \hv qr wrvhqg" write r3(0) ^[[['dwd` (send data byte) \hv qr $vnvodyhwrvhqg'dwde\wh 5hdg5! 5hdg$fnelw 5! " \hv qr1dn qr $fn 3%xv\ " \hv 5hdg5 ^[[[[[[[['dwd` 5hdg'dwde\wh \hv qr 5hfhlyhpruhe\whv" :ulwh5 ^[[[[[[[[[[` $fnqrzohgjh'dwde\wh :ulwh5 ^[[[[[[[[[[` $fn'dwde\wh :ulwh5 ^[[[[[[[[[[` 1dn'dwde\wh qr 3%xv\ " \hv :ulwh5 ^[[[[[[[[[[[` 6hqgd36wrselw 1rwh 6kdghgeorfnvduhh[hfxwhglqvriwzduh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 0qvg if a stop condition is detected at any point, the hardware resets the slave bit (r3(0)) and releases the i 2 c bus. )ljxuh 6odyh0rgh 67$57 36wduwfrqglwlrq ghwhfwhg \hv qr $gguhvvpdwfkhv \hv qr 6hwvodyhprgh5d! +rogwkhexv 6wuhwfkforfn 1dn0dvwhu :ulwh5 ^[[[[[[[[[[` 5hdg5! $fnpdvwhu ,jqruhpdvwhu :ulwhiudph 5hdgiudph r3(0)<0>=1 5! 5hvhwvodyhexv\5! 6hqggdwd write r3(0) ^[[['dwd` 5hdg5! qr1dn \hv$fn krogwkhexv vwuhwfkforfn $fnpdvwhu :ulwh5 [[[[[[[[[[ *hw'dwd 5hdg5 jrwr$fn0dvwhu 6odyh %xv\ 5d! \hv qr 5d! yes qr 5d! \hv qr 5hvhw5! 6hw5! 5:elw $fn0dvwhu :ulwh5 ^[[[[[[[[[[` $fn " 1dnpdvwhu :ulwh5 [[[[[[[[[[ 5hvhw5d! 6odyh %xv\ 6odyh %xv\ 1rwh 6kdghgeorfnvduhh[hfxwhglqvriwzduh :dlwkhuhiru3vhqg iluvwe\whfrppdqg :dlwiru$fn iurppdvwhu krogwkhexv vwuhwfkforfn
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 2q6fuhhq'lvsod\26' the z90356 provides sophisticated on-screen display features. on-screen display has the following two modes: ? osd used to generate tv control osd ? ccd used to display closed caption information osd mode provides access to the full set of control attributes including latched and unlatched attributes. unlatched attributes can be modified on a character-by-character basis. control characters change latched attributes. any 256-character set can be displayed with many display attributes, including underlining, italics, blinking, eight foreground and background colors, character position offset delay, and background transparency. a 16-bit display character represents foreground color, background color, and underline attributes, which can be modified character by character. in addition, the Z90351 supports eight fixed plus eight programmable color palettes out of 64 colors, independent left and right shadows with color control. shadows are available on transparent and nontransparent backgrounds. semitransparency is supported on a character-by-character basis. a characters pixel array is stored as 16, 18, or 20 words in character generation rom (cgrom). additional hardware provides the capability to display characters at two and three times normal size. the smoothing logic contained in the on-screen display improves the appearance of two and three times normal size characters. shadows can be activated to improve the visibility of characters by adding a border (one pixel wide) on each side. the Z90351 provides rgb signals and video blank signal. rgb outputs are available in two modes: digital and analog. in digital mode, the output rgb signals correspond to a primary colors palette. analog mode supports 16 different palettes, which can be chosen under software control. in analog mode, each rgb output is generated by a 2-bit digital- to-analog converter. the user can switch the 2-bit digital inputs of the digital-to-analog converter to port pins (p10, p13, p14, p15, p18 and p08) under software control by setting a bit in the control register. video synchronization is normally obtained from h_flyback and v_flyback but can be generated by the z90356 and driven to the external deflection unit using the bidirectional sync ports when external video synchronization signals are not present. osd is completely software controlled. hardware supports the optimum generation of the character-based os; however, the cpu can bypass it and generate pixels and attributes directly. the block diagram in figure 18 illustrates the osd data flow. figure 19 and figure 20 indicate the v1, v2, v3, and blank output circuits.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh 'dwd)orz )ljxuh %odqndqg9992xwsxwvlq'ljlwdo0rgh shift register r g b memory rd r3(3) r4(3) r3(3) r0(3) r1(3) r2(3) r0(3) r1(3) r2(3) r6(3) r7(3) cpu video ram osd:at7ch8 or attr15 ccd:char7 orattr7 cgrom pixels: 1x 2x 3x full attrib attribute p a l e t t e s 3 x d a c 9 && 3$' 3 1 2xwsxw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh 99dqg92xwsxwvlq$qdorj3dohwwh0rgh &orvhg&dswlrq'dwd&dswxuh closed-caption text can be decoded directly from the composite video signal using the processors digital signal processing capabilities and displayed on the screen. the character representation in this mode provides simple attribute control by inserting control characters. each word of video ram specifies two displayed characters. the 4-bit flash a/d converter, with proper clamping, provides the ability to receive the composite video signal directly and process the closed-caption text embedded in the signal. signal processing can be applied directly to the signal to improve decoder performance. &*5205horfdwlrq cgrom can be placed anywhere in the 64k rom address space by setting the cgrom address offset register r7(2). this offset is added to the cgrom address before accessing the rom. by modifying the cgrom offset, several fonts can be accessed (limited only by rom size). when reset, r7(2) = 0 (no offset), making the Z90351 backward- compatible with existing osd control software. 9 && 9 && 3$' 5 ? . , ? p$ , 9[! 9[! 9 && ,
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& the character scan line from cgrom addressed by the character register is fetched and stored into the cgrom capture register. if a pixel is set to 1 , it displays the foreground color. if a pixel is set to 0 , it displays the background color. the scan line can be stretched by the character multiplier to be two or three times normal character size by duplicating each bit in the word. &rqwuroolqj&kdudfwhu([sdqvlrq the character size can be stretched to two or three times its size the size of the scan line. hardware fetches data from cgrom and stretches the data to be read from registers r0(3), r1(3), and r2(3). figure 21 is a block diagram of the structure of the character expansion multiplexor, and table 11 lists bit functions. )ljxuh &kdudfwhu([sdqvlrq 7deoh &kdudfwhu([sdqvlrq5hjlvwhu &dswxuh 5hjlvwhu &rqwhqwv &kdubpxowbkljk &kdubpxowbplg &kdubpxowborz [rshudwlrq abcdefghijklmnop [rshudwlrq aabbccddeeffgghh iijjkkllmmnnoopp &*520gdwd fdswxuhuhjlvwhu &kdudfwhu ([sdqvlrq 0xowlsoh[ru fkdubpxowbplg fkdubpxowbkljk fkdubpxowborz 520gdwd 3urfhvvru(;7(51$/exv frqwuro [[[ 5 5 5
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 'lvsod\hg'dwd)rupdwv the z90356 hardware supports the following two different data formats: ? osd mode, r4(3) = 1 supports a standard osd with full set of features. ? ccd mode, r4(3) = 0 supports reduced features which comply with the recommendations of the fcc on closed caption support. in ccd mode, the background color of the characters cannot be changed and is always preset to black . 26'0rgh in osd mode, each character occupies a 16-bit word in vram. there are two possible character formats defined: a display character and a control character. the code stored in display character format defines a character code and up to 7 attributes of the character. the control character defines latched attributes and is presented on-screen as a space character. the combination of display and control characters provides versatile osd generation. smoothing is supported for double-size (x2) and triple-size (x3) characters only. &&'0rgh in ccd mode, each character occupies 8 bits (one byte) in vram. the ccd characters must be mapped into a 16-bit vram data field. the hardware supports compressed placement of characters in vram. each word in vram is represented by a high byte and a low byte. a currently active byte is selected by r4(3). the format and data representation in both bytes is exactly the same. there are two possible character formats defined: a display character and a control character. the code stored in display character format defines a character code. the control character defines up to five attributes (foreground color, italic, underline, blinking, and transparent). it is presented on screen as a space character. the combination of display and control characters provides the basis for a specified range of attributes defined by fcc specifications for ccd. [rshudwlrq aaabbbcccdddeeef ffggghhhiiijjjkk klllmmmnnnoooppp 7deoh &kdudfwhu([sdqvlrq5hjlvwhu &rqwlqxhg &dswxuh 5hjlvwhu &rqwhqwv &kdubpxowbkljk &kdubpxowbplg &kdubpxowborz
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6kdgrzv shadows, if enabled, are active on both transparent and nontransparent backgrounds. two bits in the attributewr and attributerd registers (r2(3)<1:0> and r3(3)<1:0>) control the type of shadow. refer to figure 22. )ljxuh 7deoh6hwwlqjv the smoothing attribute has been moved to r7(3)<5>. the bit assignment in the latched attribute follows the bit assignment in r2(3). the left and right shadow colors are independently controlled by r6(2) and r6(2). 0qvg the smoothing control bit r7(3)<5> must be set to a 1 in order to activate fringing. 6hpl7udqvsduhqw both semi-transparency (pin name sovl) and transparency (pin name ovl) attributes are supported. the semi-transparency mode can be enabled through either latched or unlatched attributes. latched attributes remain set until they are reset. unlatched attributes remain set for only one character, which means the attribute must be constantly refreshed on a character-by-character basis. $fwlydwlrq to activate semi-transparency output, two bits must be set properly. port 0f must be in output mode [r6(0) = 0], and the sovl/port0f control bit must be in sovl mode [r3(1)<6> = 1]. /dwfkhg6hpl7udqvsduhqf\ the latched semi-transparency attribute is controlled by bit [r2(3)<6>]. %dfnjurxqg )ruhjurxqg 5ljkwvkdgrz /hiwvkdgrz 5! 5! )xqfwlrq 1rvkdgrzv /hiwvkdgrz 5ljkwvkdgrz %rwkvkdgrzviulqjlqj
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 8qodwfkhg6hpl7udqvsduhqf\ the unlatched semi-transparency attribute is controlled by bit [r3(3)<8>]. this bit has one of four possible assignments depending on how it is set up in [r7(3)<7:6>]. the four assignments are underline, semi-transparency, blinking, and cgrom bank select. 0qvgu 1. the semi-transparency signal (svblank), when active, is only valid with the background color. with the foreground color, svblank is inactive. therefore, characters do not take on a semi-transparent appearance (only the background does). this condition allows characters to be read without interference. 2. if both the transparency (background and foreground color are equal) and semi- transparency are activated, the transparency takes precedence over the semi- transparency. the vblank signal is high, and the svblank signal is low. $wwulexwhb$vvljqphqw depending on r7(3)<7:6>, bit 8 of the attribute_data register, r3(3) (in character mode) can be assigned to control either 1st underline, semi-transparency, blinking, or cgrom bank select, as indicated in table 12. &xuvru the cursor is a one-line pixel buffer. the cursor buffer is loaded via the dma on every line where the cursor is displayed (no software support is required). horizontal size is programmable at 16, 32, or 48 pixels wide, and vertical size is programmable from 1 to 63 lines per field. the color depth is 2 bits per pixel, 3 programmable colors and the transparency. depending on r1(0), the cursors colors can be selected either from a current palette (r1(0) = 0) or from palette #6 (r1(0) = 1). refer to table 15. the cursor image is stored in rom as a bitmap. the number of cursors is limited by rom size only. the cursor is positioned by initializing cursor parameters in the beginning of every field. 7deoh $wwulexwh$vvljqphqw 5! 5! vwxqghuolqh325 6hplwudqvsduhqf\ %olqnlqj &*520edqnvhohfw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization occurs by setting the cursor_info_load bit r7(3)<4> to 1 , then writing sequentially to the r3(3) 16-bit parameters (color, hparam, vparam and caddr, respectively). the cursor buffer is loaded from rom at the leading edge of hsync wherever the horizontal line requires a cursor. this process halts the cpu for 3/5/7 cycles depending on the cursors horizontal size. the cursor bitmap address pointer (caddr) is incremented automatically. though the cursor can be displayed anywhere on the screen, limiting the cursor to the osd area is best. outside of the osd area, the cursor can jitter or become distorted. the cursor bitmap is organized as pixel data placed sequentially in the rom. the data format is described below. for the interlaced mode, even and odd cursor bitmaps must be defined separately. proper selection occurs during the cursor initialization at the beginning of every field. see figure 23, table 13, and table 14. )ljxuh &xuvru ([dpsoh ld sr,%#60; select regbank3 or ext7,#%0010; enable cursor_info_load ld ext3,#(3*64 + 7*8 + 2); load ccolor: color3 = 3, color2 = 7, color1 = 2 ld ext3,#(2*1024 + 120); load hparam: hsize = 2 (32 pixels), hpos = 120 ld ext3,#(28*1024 + 55); load vparam: vsize = 28, vpos = 55 ld ext3,#%6000; load caddrcursor bitmap address and ext7,#%ffef; disable cursor_info_load, ready for osd sl[hovpd[ olqhvpd[ froru froru froru wudqvsduhqw +rul]rqwdosrvlwlrq; 9huwlfdo srvlwlrq < )rfxv ;< lqsurjuhvvlyh vfdqprgh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh &xuvru3dudphwhuv 3dudphwhu 5hjilhog %lwsrvlwlrq 'dwd 'hvfulswlrq &$''5 &$''5 fedcba9876543210 '''' &xuvruelwpdsdgguhvv srlqwhuwrfxuvruelwpdslq520 93$5$0 96,=( fedcba---------- 9huwlfdov l]holq hvlqrqhilhog 9326 ------9876543210 9huwlfdosrvlwlrqolqhvlqrqhilhog +3$5$0 qd fedc------------ qd 5hvhuyhg +6,=( ----ba---------- 1rfxuvru sl[hovzlgh sl[hovzlgh sl[hovzlgh +326 ------9876543210 +rul]rqwdosrvlwlr qsl[hoviurp wudlolqjhgjhri+6<1& &&2/25 qd fedcba9--------- qd 5hvhuyhg &roru -------876------ &xuvru&rorudvvljqphqw &roru ----------543--- &xuvru&rorudvvljqphqw &roru -------------210 &xuvru&rorudvvljqphqw 7deoh 0hpru\$oorfdwlrqiru&xuvru?v%lwpds 3l[hov:lgh0rgh addrn: l0_p15_b0, l0_p14_b0, l0_p13_b0, ... , l0_p1_b0, l0_p0_b0 addrn+1: l0_p15_b1, l0_p14_b1, l0_p13_b1, ... , l0_p1_b1, l0_p0_b1 addrn+2: l1_p15_b0, l1_p14_b0, l1_p13_b0, ... , l1_p1_b0, l1_p0_b0 addrn+3: l1_p15_b1, l1_p14_b1, l1_p13_b1, ... , l1_p1_b1, l1_p0_b1 .................................................. addrn+2n: ln_p15_b0, ln_p14_b0, ln_p13_b0, ... , ln_p1_b0, ln_p0_b0 addrn+2n+1: ln_p15_b1, ln_p14_b1, ln_p13_b1, ... , ln_p1_b1, ln_p0_b1 3l[hov:lgh0rgh addrn: l0_p31_b0, l0_p30_b0, l0_p29_b0, ... , l0_p17_b0, l0_p16_b0 addrn+1: l0_p31_b1, l0_p30_b1, l0_p29_b1, ... , l0_p17_b1, l0_p16_b1 addrn+2: l0_p15_b0, l0_p14_b0, l0_p13_b0, ... , l0_p1_b0, l0_p0_b0
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& addrn+3: l0_p15_b1, l0_p14_b1, l0_p13_b1, ... , l0_p1_b1, l0_p0_b1 addrn+4: l0_p31_b0, l0_p30_b0, l0_p29_b0, ... , l0_p17_b0, l0_p16_b0 addrn+5: l0_p31_b1, l0_p30_b1, l0_p29_b1, ... , l0_p17_b1, l0_p16_b1 .................................................. addrn+4n: ln_p31_b0, ln_p30_b0, ln_p29_b0, ... , ln_p17_b0, ln_p16_b0 addrn+4n+1: ln_p31_b1, ln_p30_b1, ln_p29_b1, ... , ln_p17_b1, ln_p16_b1 addrn+4n+2: ln_p15_b0, ln_p14_b0, ln_p13_b0, ... , ln_p1_b0, ln_p0_b0 addrn+4n+3: ln_p15_b1, ln_p14_b1, ln_p13_b1, ... , ln_p1_b1, ln_p0_b1 3l[hov:lgh0rgh addrn: l0_p47_b0, l0_p46_b0, l0_p45_b0, ... , l0_p13_b0, l0_p32_b0 addrn+1: l0_p47_b1, l0_p46_b1, l0_p45_b1, ... , l0_p33_b1, l0_p32_b1 addrn+2: l0_p31_b0, l0_p30_b0, l0_p29_b0, ... , l0_p17_b0, l0_p16_b0 addrn+3: l0_p31_b1, l0_p30_b1, l0_p29_b1, ... , l0_p17_b1, l0_p16_b1 addrn+4: l0_p15_b0, l0_p14_b0, l0_p13_b0, ... , l0_p1_b0, l0_p0_b0 addrn+5: l0_p15_b1, l0_p14_b1, l0_p13_b1, ... , l0_p1_b1, l0_p0_b1 addrn+6: l0_p47_b0, l0_p46_b0, l0_p45_b0, ... , l0_p33_b0, l0_p32_b0 addrn+7: l0_p47_b1, l0_p46_b1, l0_p45_b1, ... , l0_p33_b1, l0_p32_b1 .................................................. addrn+6n: ln_p47_b0, ln_p46_b0, ln_p45_b0, ... , ln_p33_b0, ln_p32_b0 addrn+6n+1: ln_p47_b1, ln_p46_b1, ln_p45_b1, ... , ln_p33_b1, ln_p32_b1 addrn+6n+2: ln_p31_b0, ln_p30_b0, ln_p29_b0, ... , ln_p17_b0, ln_p16_b0 addrn+6n+3: ln_p31_b1, ln_p30_b1, ln_p29_b1, ... , ln_p17_b1, ln_p16_b1 addrn+6n+4: ln_p15_b0, ln_p14_b0, ln_p13_b0, ... , ln_p1_b0, ln_p0_b0 addrn+6n+5: ln_p15_b1, ln_p14_b1, ln_p13_b1, ... , ln_p1_b1, ln_p0_b1 7deoh 0hpru\$oorfdwlrqiru&xuvru?v%lwpds &rqwlqxhg
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& where &roru3dohwwh$vvljqphqw the z90356 features a total of 16 color palettes, 8 of which are fixed and 8 of which are programmable. palettes are selected by setting r7(3)<3:0>. fixed palettes are defined in table 15. programmable palettes (8C15) are mapped to ar0Car63 (8 registers per palette). the register and bit assignments for palette # 11 are listed in figure 24. programmable palettes are grouped into 2 banks (palettes 8C11 and 12C15). palettes in the bank cannot be modified if another palette from the same bank is displayed. if on-the-fly palette modifications are required, an interleaving palette bank access must be created. one palette bank is used to display four colors, and the other bank is used for updates. see figure 24. /[b3\b%] olqh;sl[ho<elw= /lqh iluvwwrsfxuvru?volqh 3l[ho iluvwohiwfxuvru?vsl[ho %lw%lw prvwdqgohdvwvljqlilfdqwelwriwkhfxuvru?vfrorughilqhgdv wudqvsduhqw &roru &roru &roru 7deoh )l[hg3dohwwh&roru$vvljqphqw &rorulv%odfn&rorulv:klwh 3dohwwh 'hvfulswlrq &roru &roru &roru &roru &roru &roru 5*%5*%5*%5*%5*%5*% 'ljlwdo5*% $qdorj5*% *uh\vfdohb *uh\vfdohb 5*%b&\dqb*uh\ 5*%b0djhqwdb*uh\ 5*%b =520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh 3urjudppdeoh3dohwwh&rqwurodw$55hjlvwhu 2wkhu)xqfwlrqv 9lghrdqg6rxqg$wwulexwh&rqwuro basic receiver functions such as color and volume can be controlled directly by six 6-bit pulse-width modulated ports. ,qiud5hg&dswxuh)xqfwlrq the infrared remote control data capture feature uses a capture register to hold the time value from one transition of ir data to the next. software periodically checks and reads the capture status and the value if a new capture occurs. subsequent decoding and command passing of the received ir signal is under software control. figure 25 illustrates the ir input circuit. )ljxuh ,5&dswxuh5hjlvwhu,qsxw /rrs)lowhu the loop filter pin configuration is represented in figure 26. &roru 0 1 2 3 4 5 % * 5 &roru 0 1 2 3 4 5 % * 5 &roru 0 1 2 3 4 5 % * 5 &roru 0 1 2 3 4 5 % * 5 &roru 0 1 2 3 4 5 % * 5 &roru 0 1 2 3 4 5 % * 5 $5 $5 $5 $5 $5 $5 &roru 0 1 2 3 4 5 % * 5 $5 &roru 0 1 2 3 4 5 % * 5 $5 6 7 1$ 6 7 1$ 6 7 1$ 6 7 1$ 6 7 1$ 6 7 1$ 6 7 1$ 6 7 1$ 3$' ,5,qsxw w
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh /rrs)lowhu3lq&rqiljxudwlrq +dugzduh$ffhohudwhg%lwdqg%lw6kliwv hardware-accelerated byte and nibble shifts significantly reduce software overhead. shifts are created by assigning one particular ram location (%1fe) a special meaning. depending on the r4(1) settings data read from this address is either unmodified, rotated 4 bits left, 4 bits right, or byte swapped. see table 16. ([dpsoh ld sr,#%20; select regbank1 ld a,ext4 ; turn hardware-supported shift mode on 7deoh 5hg!6hwwlqjv 5hg! )xqfwlrq 'luhfwxqprglilhg325 elwohiwurwdwh elwuljkwurwdwh %\whvzds 3$' w 3'3srvlwlyhrxw 3'3qhjdwlyhrxw 7r9&2gulyhu 9 && 9 &&
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& and a, #%9fff; or a, #%4000; ld ext4, a ; select 4-bit right rotate ld a, #%3ed7; load a = %3ed7 ld %1fe, a; write a to the ram ld a, %1fe; a = %73ed ld a,ext4; turn hardware-supported rotate mode on or a,#%6000; ld ext4, a; select byte swap ld a, %1fe; a = %d73e 5hjlvwhu*urxsv table 17 provides a summary of the registers in external banks. 7deoh 5hjlvwhu6xppdu\ %$1. %$1.6xe $gguhvv 5($'5hjlvwhu :5,7( 5hjlvwhu 'hvfulswlrq %dqn glu elw,2sruwgluhfwlrqfrqwuro glu elw,2sruwgluhfwlrqfrqwuro sruw elw,2sruw sruw elw,2sruw , &blqw , &lqwhuidfhuhjlvwhu soobiuht 3//iuhtxhqf\frqwuro zulwhfrqwurouhjlvwhu &xuvrusdohwwhjdxjh:ulwhfrqwurouhjlvwhu 5hvhuyhg 5hvhuyhg %dqn zgwbvpubfwo,qwhuuxsw 605dqg:'7frqwurodqglqwhuuxsw forfnbfwo &orfnfrqwurovzlwfk9&2'27 fdsbvbfwo &rxqwhuwlphuvfrqwuro $'&bfwo $'frqyhuwhufrqwuro vwdqgdugbfwo 2xwsxw+96<1&eoqnfrqwuro elwfrxqwhu 6723:'7 6wrsdqg:'7lqvwuxfwlrqvelwfrxqwhu vfonbiuht 6wrsvohhsqrupdoprgh fodpsbsrv 'hilqhvsrvlwlrqriylghrfodpssxovh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 5hjlvwhu'hvfulswlrq the register file in the z90356 is organized into four banks that can be selected by writing to bits 5 and 6 (register bank selector bits) in the status register of the z90356 core. all registers are mapped into an external register space; each bank consists of 8 registers. the status register is available to read or write at any time. the appropriate bank of registers must be selected before accessing the register. the software must keep track of which register bank is accessible at any time. refer to table 18 for register bank assignments. %dqn &*520riivhwuhjlvwhu &*520riivhwuhjlvwhu 6kdgrz&rqwurouhjlvwhu 'hilqhvuljkwdqgohiwvkdgrzfroru szpbgdwd elw3:0gdwd szpbgdwd elw3:0gdwd szpbgdwd elw3:0gdwd szpbgdwd elw3:0gdwd szpbgdwd elw3:0gdwd szpbgdwd elw3:0gdwd %dqn rxwsxwsdohwwh 2xwsxwsdohwwh sdohwwhbfroru 'lvsod\sdohwwhfroruxqghuolqhfroru fdswxuhbgdwd , &vodyhdggu &dswxuhuhjlvwhugdwd rvgbfrqwuro 2qvfuhhqglvsod\frqwuro dwwulexwhbgdwd yudpbgdwd &kdudfwhudwwulexwhylghr5$0gdwd fkb[borb[ fjbdwwulexwh &kdudfwhupxowlsohfkdudfwhujudsklfv dwwulexwh orb[bplgb[ fjbq[wbsuy &kdudfwhupxowlsohqh[wrusuhylrxvgdwd klb[bklb[ fjbfxuuhqw &kdudfwhupxowlsohfxuuhqwgdwd 7deoh 5hjlvwhu6xppdu\ &rqwlqxhg %$1. %$1.6xe $gguhvv 5($'5hjlvwhu :5,7( 5hjlvwhu 'hvfulswlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& %dqn,23ruwv, &,qwhuidfh3//)uhtxhqf\&xuvru&rqwuro5hjlvwhuv table 19 defines the bits for register1Cr1(0) cursor palette control register. table 20 defines the bits for register2Cr2(0) pll frequency data register. 7deoh%dqn$vvljqphqwv %dqn 6wdwxv5hjlvwhu %dqn)xqfwlrqv %dqn xxxx xxxx x00x xxxx b ,2sruwv, &lqwhuidfh3//iuhtxhqf\fxuvru %dqn xxxx xxxx x01x xxxx b &rqwurouhjlvwhuv %dqn xxxx xxxx x10x xxxx b 3:03:0 %dqn xxxx xxxx x11x xxxx b 26'sdohwwhfrqwuro 7deoh 5hjlvwhu5&xuvru3dohwwh %lw 5: 5: 5: 5: 5: 5: 5: 5: 49 5hvhw [ [ [ [ [ z %lw 5: 5: 5: 5: 5: 5: 5: 5: 49 5hvhw [ [ [ [ [ [ [ z 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg fe-------------- 5 : 5hvhuyhg 1rhiihfw &xuvru3dohwwh --d------------- : 3dohwwhuhfrpphqghg &xuuhqwsdohwwh2325 3j:ulwhq(q ---c------------ 5: 3djh:ulwh(qdeoh 3djh:ulwh'lvdeoh2325 3djh:ulwh ----ba9876543210 5 : [[[[ :ulwh3djh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& if the master or slave i 2 c interface is enabled, the corresponding i/os (port01 and port02 for the slave, port11 and port12 for the master) must be assigned as outputs. the vco, dot, and sclk frequency are defined as the following: f vco = f dot = f sclk = xtal * (256 + pll data ) therefore, xtal = 32.768 khz . 7deoh 5hjlvwhu53//)uhtxhqf\'dwd5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 0bglvdeoh f--------------- 5: , &0dvwhulqwhuidfhglvdeohg , &0dvwhulqwhuidfhhqdeohg325 6bglvdeoh -e-------------- 5: , &6odyhlqwhuidfhglvdeohg , &6odyhlqwhuidfhhqdeohg325 , &0bpx[ --d------------- 5: 6hohfw, 06', 06&325 6hohfw, 06', 06& , &b2xwb 5hvlvwdqfh ---c------------ 5: w rxwsxwuhvlvwdqfh 1rupdo&026sruwrxwsxw uhvlvwdqfh325 , &bvshhg budqjh ----b----------- 5: /rzvshhgudqjhn+]n+] +ljkvshhgudqjhn+] n+]325 5hvhuyhg -----a---------- 5 : 5hwxuq3 1rhiihfw 3 +6<1& ------9--------- 5: +6<1&orjlfwdnhvlqsxwiurp3lq +6<1&orjlfwdnhvlqsxwiurp +6<1&slq325 3 &rp6<1& -------8-------- 5: &rpsrvlwh6\qf2xwsxw 3,2325 3//bgdwd --------76543210 5 : [[ 3//glylghu [[
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& at por, the pll frequency data register is preset to %70, which corresponds to the vco frequency of 12.058 mhz. the pll_data field can be loaded with any value from %00. this value corresponds to an sclk = 256*xtal up to %ff, which corresponds to an sclk = 511*xtal. table 21 through table 25 describe the bits in registers 3 through 7.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& data written to r3(0) requires 4 cycles before being applied. consecutive writings to these bits require at least a 6-cycle delay. the received data is available for reading only when the busy bit is reset to a 0. when por, the speed of the i 2 c interface is set to low. 7deoh 5hjlvwhu5, &,qwhuidfh5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq &rppdqg fed------------- 5 :' 5hwxuq 6hh7deohdqg7deohirudixoo ghvfulswlrq 7rjjoh ---c------------ 5 : 6odyhlqwhuidfh 0dvwhulqwhuidfh325frqglwlrq 7rjjohdfwlyh, &lqwhuidfh 1rhiihfw 5hvhw ----b----------- 5 : 5hwxuq 5hvhw6odyh, &lqwhuidfhlielwf! 5hvhw0dvwhu, &lqwhuidfhlielwf! 1rhiihfw 6odyhbprgh -----a---------- 5 : 6odyhprghlvdfwlyh325frqglwlrq 6odyhprghlvlqdfwlyh 1rhiihfw 6odyh%xv\ ------9--------- 5 : 6odyh, &lqwhuidfhlvexv\ 6odyh, &lqwhuidfhlvlgoh 1rhiihfw 0dvwhu%xv\ -------8-------- 5 : 0dvwhu, &lqwhuidfhlvexv\ 0dvwhu, &lqwhuidfhlvlgoh 1rhiihfw 'dwd --------76543210 5 : [[ [[ 5hfhlyhggdwd 'dwdwrehvhqw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh 5hjlvwhu53ruw'dwd5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 3ruwbgdwd fedcba9876543210 5 : [[[[ [[[[ ,idsruwlvfrqiljxuhglq,qsxw prghhqwhuwkhlqsxwgdwdrqwrwkh sruwslqv ,idsruwlvfrqiljxuhglq2xwsxw prghwkhqwkhgdwdlvzulwwhq gluhfwo\wrwkhsruwgdwd
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh 5hjlvwhu53ruw'dwd5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg fedcba9--------- 5 : 5hwxuq 1r(iihfw 3ruwbgdwd -------876543210 5 : [[[[ [[[[ ,idsruwlvfrqiljxuhglq,qsxw prghhqwhuwkhlqsxwgdwdrqwrwkh sruwslqv ,idsruwlvfrqiljxuhglq2xwsxw prghwkhqwkhgdwdlvzulwwhq gluhfwo\wrwkhsruwgdwd 7deoh 5hjlvwhu53ruw'luhfwlrq5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 3ruwbgluhfwlrq fedcba9876543210 5 : [[[[ ,qsxwprghiru fruuhvsrqglqjelw 2xwsxwprghiru fruuhvsrqglqjelw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& %dqn&rqwuro5hjlvwhuv table 26 through table 33 provide bit functions for bank 1 control registers. 7deoh 5hjlvwhu53ruw'luhfwlrq5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg fedcba9--------- 5 : 5hwxuq 1r(iihfw 3ruwbgluhfwlrq -------876543210 5 : [[[[ ,qsxwprghiru fruuhvsrqglqjelw 2xwsxwprghiru fruuhvsrqglqjelw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& at por the disable_clamp bit is set to 1 . 7deoh 5hjlvwhu5&odps3rvlwlrq5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 'lvdeohbfodpsb f--------------- 5: $'&&odpsjhqhudwlrqlv glvdeohg $'&&odpsjhqhudwlrqlv hqdeohg 'lvdeohbfodpsb -e-------------- 5: $'&&odpsjhqhudwlrqlv glvdeohg $'&&odpsjhqhudwlrqlv hqdeohg 'lvdeohbwlsbfodps --d------------- 5: $'&7lsfodpslvglvdeohg 325 $'&7lsfodpslvhqdeohg &rxqwhublqsxw ---c------------ 5: &rxqwhuwdnhvlqsxwiurp 3325 &rxqwhuwdnhvlqsxwiurp lqwhuqdo+6<1&6hsdudwru $5hqdeoh ----b----------- 5 : $5hqdeohg $5glvdeohg325 5hvhuyhg -----a987------- 5 : 5hwxuq3 1rhiihfw 3rvlwlrq ---------6543210 5 : [[ 3rvlwlrqrifodpssxovhiurp ohdglqjhgjhriwkh+ )/<%$&.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& the clamp pulse is generated if enabled (bit ) and the sclk frequency are switched back to pvco. the svco/pvco flag in r6(1) must be reset to 0 before the current hsync, regardless of whether the svco is enabled or disabled. the clamp position is defined by the position field. the width of the clamp pulse cannot be modified and is set to 1us. the value that can be assigned to the position field must be >%10 and <%7f. the time interval between the leading edge of the h-flyback and the beginning of the clamp pulse can be calculated from the following equation: when a por, smr, or wdt reset occurs, both the fast_enable and fast/slow are reset to 0 . this event corresponds to an sclk frequency of 32.768 khz. to switch from a 32.768-khz sclk to 12 mhz, use the following procedure: 1. set the h_position field r6(1)<3:0> to a nonzero value. 2. enable the primary and secondary vcos (set the fast_enable bit r1(1)<1> to 1). 7deoh 5hjlvwhu56shhg&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg fedcba98765432-- 5hvhuyhg5hwxuq )dvwbhqdeoh --------------1- 49 39&269&2hqdeohg 39&269&2glvdeohg325 )dvwbvorz ---------------0 49 6&/.lv0+] 6&/.lv.+]325 t delay positio n 1 tsclk - - - - - - - - - y ?? position 82ns ? ==
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 3. wait for one second (1s) for the 12-mhz pll to stabilize (about 50000 clock cycles). the delay depends on the external pll filter and can vary significantly. 4. switch the sclk to a fast clock (set fast/slow bit r1(1)<0> to 1 ). 5. simultaneously set the h_position field r6(1)<3:0> to 0fh and the no_switch field r6(1)<4> to 1 (no clock switch). to switch from the 12-mhz sclk to 32.768 khz, use the following procedure: 1. switch the sclk to a 32.768-khz clock (set fast/slow bit r1(1)<0> to 0 ). 2. wait for more than r2(0)<7:0> + 256 clock cycles (approximately 32 m s) for the sclk to be switched. 3. set the hsync_delay field r6(1)<3:0> to 0fh . 4. disable the primary and secondary vcos (set the fast_enable bit r1(1)<1> to 0 ). 7deoh 5hjlvwhu5:'76723zulwhrqo\dqg %lw&rxqwhuuhdgrqo\&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq &rxqwhubydoxh fedcba987------- 5 : &rxqwhurq3ruwydoxh 1rhiihfw 5hvhuyhg ---------65432-- 5 : 5hwxuq 0 1rhiihfw :'7blqvwu --------------1- 5 : 5hwxuq 0 :'7hqdeoh:'7uhvhw 1rhiihfw 6723blqvwu ---------------0 5 : 5hwxuq 6wrs 1rhiihfw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& when a por, smr or a wdt reset occurs, the wdt is disabled. the wdt can be reenabled only after the pvco and svco are enabled, and the part is switched into a fast mode (sclk = 12 mhz). when switching the part into a slow mode (sclk = 32.768 khz), the wdt halts. to return to fast mode, the wdt must be initialized again. 7deoh 5hjlvwhu56wdqgdug&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq &rxqwhubuhvhw f--------------- 5 : 5hwxuq 5hvhw&rxqwhurq3ruw 1rhiihfw &rxqwhub212)) -e-------------- 5: &rxqwhurq3ruwlv21 &rxqwhulv2))325frqglwlrq 0dvnb+96<1& --d------------- 5: 'lvdeoh+96<1&rxwsxw +96<1&,1287325frqglwlrq &kdubvl]hbb ---c------------ 5: [fkdudfwhupdwul[ [ru[fkdudfwhupdwul[ 325 $cpmaugn ----ba---------- 49 00 01 10 11 4#/$cpm 214 4#/$cpm 4#/$cpm 4gugtxgf 5*%&3ruw ------9--------- 5: 6&/.5!*!%! 3333333 , &b+,/2bvshhg -------8-------- 5: +,vshhgn+] /2vshhgn+]325
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& two bits define the polarity of the hvsync signals. bit <3> defines polarity of the signals when they are configured as outputs (it does not affect the internal hv C sync signals). bit <1> defines the polarity of the external hv C sync signals, affecting the synchronization of the device. 0qvgu 1. the composite sync is active in internal mode only. 2. when using the internally-generated composite sync signal, be sure the sclk is set to 12.09 mhz (r2(0)<7:0> = %71). this action helps ensure the best hsync frequency approximation. &*520edqn --------7------- 5: %dqnlvvhohfwhgvwduwv # %dqnlvvhohfwhgvwduwv # 69%/$1.3i ---------6------ 5: 6hplwudqvsduhqf\ 3irxwsxw 26'brqrii ----------5----- 5: 26'lvhqdeohg 26'lvglvdeohg325 5*%bsrodulw\ -----------4---- 5: 1hjdwlyh 3rvlwlyh 3rvlwlyh1hjdwlyh ------------3--- 5: 1hjdwlyh+96<1&lqrxwsxwprgh 3rvlwlyh+96<1&lqrxwsxwprgh 6<1&%/$1. -------------2-- 5: +9%/$1.rxwsxwv +96<1&rxwsxwv b+]dqg +9bsrodulw\ --------------10 5: ,qwhuqdoprgh rqo\ 796wdqgdug +]olqhvvxssruw +]olqhvvxssruw325 ([whuqdoprgh rqo\ +93rodulw\ 3rvlwlyh 1hjdwlyh 7deoh 5hjlvwhu5$'&&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 0qvg *if hsync is leading edge active (r4(1) = 1),the actual interrupt is delayed from the leading edge of hsync by 72 cycles (~6us @12mhz). 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg f--------------- 5 : 5hvhuyhg 1r(iihfw +:bvkliw -ed------------- 5 : 'luhfwxqprglilhg325 elwvkliwohiw elwvkliwuljkw %\whvzds +6<1&bhgjh ---c------------ 5: +6<1&lvohdglqjhgjhdfwlyh +6<1&lv wudlolqjhgjhdfwlyh325 $'&buhi ----b----------- 5: $'&vxvh$9 && dqg$*1'dv uhihuhqfhyrowdjh $'&vxvh9dqg9dv uhihuhqfhyrowdjh325 $'&bvhohfw -----a---------- 5: $'&$'&vhohfw $'&$'&$'&$'&vhohfw 325frqglwlrq $'&gdwd 3dfnlqj ------9--------- 5 : $'&gdwdsdfnlqjlvrq $'&gdwdsdfnlqjlvrii2325 5hvhuyhg -------8-------- 5 : 5hwxuq3 1rhiihfw $'&vshhg --------76------ 5: 6lqjohfrqyhuvlrq325frqglwlrq 6&/. 6&/. 6&/. $'&vrxufh ----------54---- 5: $'&&9,$'&3325 $'&3$'& $'&3 $'&3 $'&gdwd ------------3210 5 : ' $'&gdwd 1rhiihfw 7deoh 5hjlvwhu5$'&&rqwuro5hjlvwhu &rqwlqxhg
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& adc0 has a signal range from 1.5 to 2.0 v. this field is always connected to the composite video input pin and can be clamped to a refC voltage (1.5v). adc1, adc2, adc3, and adc4 have a signal range from 0 to 5.0 v. adc5 features a signal range from 1.5 to 2.0 v. for this field, the input signal can be clamped to a ref+ voltage (2.0v). to use the i/o pin as an adc input, the corresponding port must be set up as an input (refer to r4(0) and r6(0)). 7deoh 5hjlvwhu57lphu&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq &$3lqwbu f--------------- 5 : 5lvlqjhgjhlvfdswxuhg 1rulvlqjhgjhlvfdswxuhg 5hvhwiodj 1rhiihfw &$3lqwbi -e-------------- 5 : )doolqjhgjhlvfdswxuhg 1ridoolqjhgjhlvfdswxuhg 5hvhwiodj 1rhiihfw 7rxwbv --d------------- 5 : 7lphrxwrivwlphu 1rwlphrxwrivwlphu 5hvhwiodj 1rhiihfw 7rxwb&$3 ---c------------ 5 : 7lphrxwri&dswxuhwlphu 1rwlphrxwri&dswxuhwlphu 5hvhwiodj 1rhiihfw 5hvhuyhg ----ba---------- 5 : 5hwxuq3 1rhiihfw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6shhgbv ------98-------- 5: v pv pv pv 3ruw &$3blqw --------7------- 5: lqwvrxufhlv3ruw lqwvrxufhlv&dswxuhwlphu &$3bkdow ---------6------ 5: &dswxuhwlphulvkdowhg &dswxuhwlphulvuxqqlqj &$3bhgjh ----------54---- 5: 1r&dswxuh &dswxuhrqulvlqjhgjhrqo\ &dswxuhrqidoolqjhgjhrqo\ &dswxuhrqerwkhgjhv &$3bjolwfk ------------32-- 5: *olwfkilowhulvglvdeohg 76&/.lvilowhuhgrxw 76&/.lvilowhuhgrxw 76&/.lvilowhuhgrxw &$3bvshhg --------------10 5: 6&/. 6&/. 6&/. 6&/. 4gugvvkpic%crvwtg6kogthncifqgupqvoqfkh[%crvwtg%qwpvgtcpfqt%crvwtgtgikuvgtfcvc9jgpvjg inkvejhknvgtkugpcdngfvjgfwtcvkqpqhvjgrwnugkufgetgcugfd[%#2ainkvejxcnwg 7deoh 5hjlvwhu5&orfn6zlwfk&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg fedcba9876------ 5 : 5hwxuq 1rhiihfw 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& +b3rvlwlrq the h_position field defines the delay between when the z90356 receives an h-sync and when the h-sync interrupt is executed. because the on-screen display is controlled by software this delay allows fine tuning for on-screen display centering. at power on reset (por) this value is in an unknown state. if this value is set to 0x0, neither the h sync interrupt nor clock switching can execute. to receive an h sync interrupt, valid delay values are between 0x1 and 0xf . valid delay values produce a delay according to the following equation: 11 + 4 * (h_position - 1) for example, an h_position setting of 0xf produces a delay of 67 system clock cycles after the trailing edge of h sync . 11 + 4 * (15 - 1) = 67 1rb6zlwfk the no_switch bit determines if the system clock is permanently set to the primary vco (pvco) or allowed to switch between pvco and the secondary vco (svco). this bit is set to 1 (no clock switching) at power up reset. caution: after the system has been switched to fast (12 mhz) clock both signals feeding into this switch must be pvco before the switch setting is changed. otherwise a short system clock can result which causes the processor to run at a higher frequency than specified. the instruction fetched from memory, at the location with the out-of-spec frequency, can be corrupted! to ensure safe clocks, the following practices are recommended: 1. set the no_switch to the required setting before switching from the 32.768 khz to the fast (12 mhz) clock and leave it there permanently. 69&239&2 ----------5----- 5 : 6&/. 69&2iodj 6&/. 39&2iodj325 6zlwfk6&/.wr39&2 1rhiihfw 1rb6zlwfk -----------4---- 5: 6&/. 39&2qrforfn vzlwfklqj2325 &orfnvzlwfklqjlvhqdeohg +b3rvlwlrq ------------3210 5 : ' 'hilqhvghod\ri+ 6<1& lqwhuuxsw e\;6&/.f\fohv 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 2. use the following procedure when changing from switching vco to permanent pvco while running from the fast clock: simultaneously set the h_position delay to 0x0, while leaving the no_switch enabled (0), and the svco/pvco left as (0). wait a minimum of 80 clock cycles to flush any h-sync out of the system. simultaneously switch svco/pvco to pvco (write 1 into r6(1)<5>), while leaving the no_switch enabled (0), and the h_position delay at 0x0. wait for 3 system clock cycles to be sure that the clock has had time to switch to pvco. switch no_switch to no clock switch (write 1 into r6(1)<6>). the h_position can be set to none-zero at this time as well. 3. use the following procedure when changing from permanent pvco to switching vco while running from the fast clock. simultaneously set the h_position delay to 0x0, while leaving the no_switch disabled (1), and the svco/pvco setting as dont care (0). wait a minimum of 80 clock cycles to flush residual h-sync out of the system. simultaneously switch svco/pvco to pvco (write 1 into r6(1)<5>), while leaving the no_switch disabled (1), and the h_position delay at 0x0. wait 3 system clock cycles to be sure that the clock has had time to switch to pvco. switch no_switch to clock switching is enabled (write 0 into r6(1)<6>). the h_position can be set to none-zero at this time as well. 69&239&2 the svco/pvco bit when read back determines the current setting of the system clock. writing a 1 to this bit switches the system clock from its current setting to pvco. this switch has a glitch filter that removes random voltage spikes. it must be changed back to pvco. the z90356 switches to the svco automatically when it receives an h-sync interrupt. this mechanism exists to synchronize the system clock exactly with the h-sync trailing edge. the result is a sharp start of the osd, jitter free. an example of a typical svco/pvco switching follows: 1. system clock is set to pvco. 2. h-sync interrupt occurs. (the system clock has automatically been set to the svco). osd code is executed inside of the h-sync interrupt service routine (isr). 3. before leaving the isr, the user switches the clock back to pvco.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& the clamp pulse (defined in r0(1)) is generated only if the svco/pvco switch is set to pvco before receiving an h sync . the software provides the correct switch setting before every h sync . table 33 lists the interrupt/wdt for the wst/smr control register. 7deoh 5hjlvwhu5,qwhuuxswv:'7605&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq ,qwbsulrulw\ fed------------- 5 : [ 6hh7deoh ,qwbpdvn ---cba---------- 5 : [[ [[ [[ [[ [[ [[ lqwlvhqdeohg lqwlvglvdeohg lqwlvhqdeohg lqwlvglvdeohg lqwlvhqdeohg lqwlvglvdeohg :'7vshhg ------98-------- 5: pv pv pv pv 605iodj --------7------- 5 : 1r6wrs0rgh5hfryhu\325 6wrs0rgh5hfryhu\ 1rhiihfw 605 srodulw\ ---------6------ 5: 25ridoo605vrxufhv 1$1'ridoo605vrxufhv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& the final result of the stop-mode recovery (smr) is reset. ports selected for smr must be assigned as inputs, while the other smr ports must be assigned as outputs exhibiting an inactive value. if any smr source is active, and the stop mode is executed, the part resets immediately. all core interrupts are set to int0 > int1 > int2. these priorities cannot be changed and are embedded into the core. however, z90356 architecture provides flexibility to change the priority of the interrupts by switching the interrupt sources between interrupt inputs of the z90356 core. the correspondence between h sync , v sync and 1s/cap interrupts sources, and int0, int1, and int2 interrupts inputs of the z90356 are listed in table 34. %dqn3:05hjlvwhuv table 35 lists the bits for the pwm registers. 605vrxufh vpu vpu vpu vpu vpu vpu ----------543210 ----------5----- -----------4---- ------------3--- -------------2-- --------------1- ---------------0 5 : [[ %lwzklfkfruuhvsrqgvwrd3lq[[ elqdu\uhsuhvhqwdwlrqlvdfwlyh s s s s s s 7deoh ,qwhuuxsw3ulrulw\ ,qwb3ulrulw\ )lhog +6<1&,v 6zlwfkhg7r 96<1&,v 6zlwfkhg7r v&$3,v 6zlwfkhg7r ,qwb3ulrulw\ )lhog lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw lqw 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& all of the pwms feature push-pull. outputs from all pwms are staged by one pvco clock. the repetition frequency of the pwm output signals can be calculated from the following equation: when reset, pwm_data registers are not initialized; however, pwm output is set to 0 . because the pwm is clocked with pvco, it is better to initialize the pwm_data before enabling pvco. table 36 lists the bits for the shadow control register. table 37 lists the bits for the cgrom offset register. 7deoh 5hjlvwhu5hjlvwhu553:05hjlvwhuv %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg fedcba98-------- 5 : 5hwxuq 1rhiihfw 3:0bgdwd --------76543210 5 : [[ elw3:0gdwd f pwm f pvco 8 256 C - - - - - - - - - - - 12mhz 2048 - - - - - - - - - - 6khz ===
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh 5hjlvwhu56kdgrz&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 5hvhuyhg fe-------------- 5 : 5hwxuq 1rhiihfw /vkdgrz&roru --dcb----------- 5 : [[ /hiwvkdgrzfroru325 5vkdgrz&roru -----a98-------- 5 : [[ 5ljkwvkdgrzfroru325 5hvhuyhg --------76543210 5 : 5hwxuq 1rhiihfw 7deoh 5hjlvwhu5&*5202iivhw5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq &*riivhw fedcba9876543210 5 : [[[[ &*520riivhw325
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& %dqn2q6fuhhq'lvsod\>26'@5hjlvwhuv table 38 lists the r0(3)- r2(3) character multiplier registers (read operation). table 39 lists the r0(3)Cr1(3) shift registers (write operation). table 40 lists the r2(3) attributes register (write operation). 7deoh 5hjlvwhu5hjlvwhu5hdg2shudwlrq 55&kdudfwhu0xowlsoh5hjlvwhuv %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj1dph &*520'dwd 5hj$gg 'hvfulswlrq fjurpb[bkl fjurpb[bkl ffeeddccbbaa9988 fffeeedddcccbbba 5 +ljkzrugrigrxeohvl]hfkdudfwhu 5! +ljkzrugriwulsohvl]hfkdudfwhu 5! fjurpb[bor fjurpb[bplg 7766554433221100 aa99988877766655 5 /rzzrugrigrxeohvl]hfkdudfwhu 5! 0lggohzrugriwulsohvl]hfkdudfwhu 5! fjurpb[ fjurpb[bor fedcba9876543210 5444333222111000 5 6lqjohvl]hfkdudfwhu5! /rzzrugriwulsohvl]hfkdudfwhu 5!
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& registers r1(3) and r0(3) must be loaded with video data once every 16 cycles. to support smoothing, register r1(3) must be updated every 16 cycles. the current line register is loaded first, followed by next/previous register during the next cycle. the next/ previous register is loaded only if smoothing/fringing attributes are activated for the current character. if neither register is loaded, the space character is displayed. there is no difference between loading 0000h into either register or not loading at all. 7deoh 5hjlvwhu5hjlvwhu:ulwh2shudwlrq 556kliw5hjlvwhuv %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj1dph &*520'dwd 5hj$gguhvv 'hvfulswlrq fxuuhqwbuhj fedcba9876543210 5 fxuuhqwolqhvkliwuhjlvwhu qh[wsuhylrxvbuhj fedcba9876543210 5 qh[wsuhylrxvolqhvkliwuhjlvwhu 7deoh 5hjlvwhu25$wwulexwhv5hjlvwhu:ulwh2shudwlrq %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq 5hvhuyhg f--------------- [ 1rhiihfw
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& %dfnjurxqgfroru -edc------------ %odfn %oxh *uhhq &\dq 5hg 0djhqwd =520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 0qvg *if both the background and foreground colors of a character are set to be the same, the characters background is displayed as transparent. the attributes register must be loaded 8 cycles after the current line register r0(3) is loaded. loading the attributes register enables the osd logic during the next 16 cycles. if the attributes register is not loaded, there is no active osd, even if the current line register r0(3) is loaded. see table 41. the data read from the attribute register is a combination of attribute fields from the most recently displayed character and control character codes loaded into the attribute_data register. character codes are fetched from video ram and must be loaded into the attribute_data register r3(3). bit of the attribute_data register (during a read) indicates whether the most recent character was a control or displayed character. the data read from the attribute_data register must be directly loaded into attribute register r2(3). refer to table 42. 6kdgrzlqj)ulqjlqj --------------10 1rvkdgrzlqjqriulqjlqj /hiwvkdgrz 5ljkwvkdgrz %rwkvkdgrzviulqjlqj 7deoh 5hjlvwhu5hdg2shudwlrq 5$wwulexwhv5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq 6dphdv5 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& loading vram data into an attribute_data register initializes a cgrom access cycle. four clock cycles after the ld instruction, the z90356 halts for three clock cycles to fetch the data from cgrom and latch it into a cgrom data capture register. after the cgrom data is latched, core operations are resumed. when a control character code is loaded into the attribute_data register, the cgrom data from address 0000 hex is fetched. therefore, zilog recommends placing a space character at location 0000 hex in cgrom. refer to table 43 through table 46 for the various vram data formats loaded in r3(3). 7deoh 5hjlvwhu5:ulwh2shudwlrq $wwulexwh'dwd5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq 95$0bgdwd fedcba9876543210 [[[[ &kdudfwhufrghihwfkhgiurp95$0
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh 'lvsod\&kdudfwhu)rupdwiru$wwulexwh'dwd5hjlvwhu5 26'0rgh:ulwh2shudwlrq %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq &rqwuroelw f--------------- 'lvsod\fkdudfwhu %dfnjurxqgfroru -edc------------ %odfn %oxh *uhhq &\dq 5hg 0djhqwd =520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& smoothing is supported for double size (x2) and triple size (x3) characters only. at reset, the background color in osd mode is black. foreground color, background color, blinking and italic attributes are delayed by 3/4 character. the smoothing attribute is enabled. 7deoh &rqwuro&kdudfwhu)rupdw26'0rgh:ulwh2shudwlrq $wwulexwh'dwd5hjlvwhu5 %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq &rqwuroelw f--------------- &rqwurofkdudfwhu 5hvhuyhg -edcba98-------- [ 5hvhuyhg2grhvqrwdiihfw26' 6kliwbylghr --------7------- 9lghrvljqdolvghod\hge\sl[hov 6wdqgdugfkdudfwhusrvlwlrqlqj 7udqvsduhqw ---------6------ 7udqvsduhqwedfnjurxqg %dfnjurxqgfrorughilqhge\3edfnjurxqg froruilhog %olqnlqj ----------5----- %olqnlqjfkdudfwhu 1rweolqnlqjfkdudfwhu ,wdolf -----------4---- ,wdolffkdudfwhu 1rwlwdolffkdudfwhu &rorubghod\ ------------32-- &kdudfwhufrorufkdqjhvlqvwdqwo\ &rorufkdqjhvzlwksl[hovghod\ &rorufkdqjhvzlwksl[hovghod\ &rorufkdqjhvzlwksl[hovghod\ 6kdgrzlqj )ulqjlqj --------------10 1rvkdgrzlqjqriulqjlqj /hiwvkdgrz 5ljkwvkdgrz %rwkvkdgrzviulqjlqj
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh 'lvsod\&kdudfwhu)rupdw$wwulexwh'dwd5hjlvwhu5 :ulwh2shudwlrq&&'0rgh %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq &rqwuroelw 7------- 'lvsod\fkdudfwhu &kdudfwhufrgh -6543210 '' 'hilqhvwkhfkdudfwhulq&*520
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& in ccd mode, each character occupies 8 bits (one byte) in vram. the ccd characters must be mapped into a 16-bit vram data field. the hardware supports compressed character placement in vram. each word in vram is represented by high byte and low byte. a currently active byte is selected by r4(3). the format and data representation for both bytes is the same. there are two possible character formats defined: a display character and a control character. the code stored in display character format defines a character code. the 7deoh &rqwuro&kdudfwhu)rupdw$wwulexwh'dwd5hjlvwhu5 &&'0rgh:ulwh2shudwlrq %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 'dwd 'hvfulswlrq &rqwuroelw 7------- &rqwurofkdudfwhu 7udqvsduhqw -6------ 7udqvsduhqwedfnjurxqg %dfnjurxqgfrorughilqhge\3edfnjurxqg froruilhog %olqnlqj --5----- %olqnlqjfkdudfwhu 1rweolqnlqjfkdudfwhu ,wdolf ---4---- ,wdolffkdudfwhu 1rwlwdolffkdudfwhu )ruhjurxqgfroru ----321- %odfn %oxh *uhhq &\dq 5hg 0djhqwd =520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& control character defines up to seven attributes of the next character and is presented on screen as a space character. combining display and control characters generates a ccd or osd according to fcc specification. refer to table 47. the underline field must be set by firmware when scan lines that contain underline information are displayed. the underline bits are anded with the second and first 7deoh 5hjlvwhu2526'&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 8qghuolqh fe-------------- 5: [ [ [ [ 6hfrqgxqghuolqhlvdfwlyh 6hfrqgxqghuolqhlvlqdfwlyh )luvwxqghuolqhlvdfwlyh )luvwxqghuolqhlvlqdfwlyh 26'&&' --d------------- 5: 26'prgh &&'prgh &&'bwrsewp ---c------------ 5: 7khxsshue\whlq95$0lvxvhg 7khorzhue\whlq95$0lvxvhg ,wdolfbvkliw ----ba98-------- 5 : [ 'hilqhvghod\riwkhfkdudfwhu %olqnbriirq --------7------- 5: %olqnlqjfkdudfwhulvglvsod\hg %olqnlqjfkdudfwhulv127 glvsod\hgklgghq 03;bexv ----------65---- 5: [fkdudfwhuvl]h [fkdudfwhuvl]h [fkdudfwhuvl]h 5hvhuyhg &*520 vfdqbolqh -----------43210 5 : ' 'hilqhv&*520dgguhvvlqj
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& underline active fields of data loaded into attribute register r2(3), causing the screen character to be underlined. the italic shift field defines a delay of video data. it is used to generate italic characters. the firmware decrements by 1 (the value of the italic_shift field) for each consecutive line. the video signal is delayed only for characters that have the r2(3)<4> (italic) bit set to 1 . table 48 lists the bits for the capture register. in read mode, r5(3) returns the 16-bit captured data from the irin pin. in write mode, the 7-bit i 2 c slave interface address must be put in bit 7-1. table 49 lists the bits for the palette control register. 7deoh 5hjlvwhu5&dswxuh5hjlvwhu5hdg2shudwlrq %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw [ [ [ [ [ [ [ [ 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq &dsbgdwd fedcba9876543210 5 [[[[ elwfdswxuhggdwd 5hvhuyhg fedcba98-------0 5 : 5hwxuq 1rhiihfw ,&bvdggu --------7654321- : '' , &6odyhlqwhuidfhdgguhvv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& at por the palette control register is reset to 0 . table 50 lists the bits for the output palette control register. 7deoh 5hjlvwhu53dohwwh&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq 3dohwwh f--------------- 5: 3dohwwhprghlvdfwlyh 3dohwwhprghlv,1$&7,9( 8qghuolqh froru -edc------------ 5: %odfn %oxh *uhhq &\dq 5hg 0djhqwd =520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& at por the output palette register is set to 0 for digital output. table 15 is the look-up table for the color palettes. 7deoh 5hjlvwhu52xwsxw3dohwwh&rqwuro5hjlvwhu %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw %lw 5: 5: 5: 5: 5: 5: 5: 5: 5: 5hvhw 0qvg44gcf99tkvg:+pfgvgtokpcvg 5hj)lhog %lw3rvlwlrq 5 : 'dwd 'hvfulswlrq %/$1.bghod\ fedc------------ 5 : 9%odqndqg69%/$1.ghod\ ydoxh2325frqglwlrq %dfnjurxqgbrq rii ----b----------- 5: 0dvwhuedfnjurxqglvrq 0dvwhuedfnjurxqglvrii325 frqglwlrq %dfnjurxqgbfroru -----a98-------- 5 : ' 'hilqhvwkhfroruriwkh0dvwhu edfnjurxqgvdphdvwkh sdohwwh $wwu6hohfw --------76------ 5: vwxqghuolqh2325 6hplwudqvsduhqf\ %olqnlqj &*520edqnvhohfw 6prrwklqj ----------5----- 5: 6prrwklqjorjlfglvdeohg2325 6prrwklqjorjlfhqdeohg &xuvru:ulwh (qdeoh -----------4---- 5 : 5hwxuq3 &xuvrusdudphwhuvzulwh glvdeohg2325 &xuvrusdudphwhuvzulwh hqdeohg 3dohwwh ------------3210 5 : ' 3dohwwhqxpehu
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ,qvwuxfwlrq6hw the processor instruction set consists of 30 basic instructions. it is optimized for high code density and reduced execution time. single-cycle instruction execution is possible on most instructions. the format for op codes and addressing modes is provided in the following tables but is normally not required. the assembler removes the burden of hand constructing the instruction format. by translating the mnemonics. system designers can access the instruction format when debugging. ,qvwuxfwlrq6xppdu\ the dsp instruction set can be broken down into the following types of instructions: ? accumulator modification ? arithmetic ? bit manipulation ?load ?logical ? program control ? rotate and shift instruction format mnemonics are in table 51. table 52 through table 58 list other instructions. 7deoh ,qvwuxfwlrq)rupdw0qhprqlfv 0qhprqlf 'hvfulswlrq $ $gguhvv dp $ffxpxodwru0rglilfdwlrq e 5$0%dqn cc &rqglwlrq&rgh frqvwh[s &rqvwdqw([suhvvlrq d 'hvwlqdwlrq$gguhvv ghvw 'hvwlqdwlrq9doxh ip )odj0rglilfdwlrq rs 2s&rgh us 5hjlvwhu3rlqwhu
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& v 6rxufh$gguhvv vuf 6rxufh9doxh 7deoh $ffxpxodwru0rglilfdwlrq,qvwuxfwlrqv 0qhprqlf 2shudqgv ,qvwuxfwlrq $%6 ff!$ $evroxwh9doxh &3 $vuf! &rpsdulvrq '(& ff!$ 'hfuhphqw ,1& ff!$ ,qfuhphqw 1(* ff!$ 1hjdwh 7deoh $ulwkphwlf,qvwuxfwlrqv 0qhprqlf 2shudqgv ,qvwuxfwlrq $'' ff!$ $gg &3 $vuf! &rpsduh 68% $vuf! 6xewudfw 7deoh %lw0dqlsxodwlrq,qvwuxfwlrqv 0qhprqlf 2shudqgv ,qvwuxfwlrq &&) 1rqh &ohdu&duu\)odj &,() 1rqh &ohdu,qwhuuxsw(qdeoh)odj &23) 1rqh &ohdu2yhuiorz3urwhfwlrq)odj 6&) 1rqh 6hw&duu\)odj 6,() 1rqh 6hw,qwhuuxsw(qdeoh)odj 623) 1rqh 6hw2yhuiorz3urwhfwlrq)odj 7deoh ,qvwuxfwlrq)rupdw0qhprqlfv &rqwlqxhg 0qhprqlf 'hvfulswlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh /rdg,qvwuxfwlrqv 0qhprqlf 2shudqgv ,qvwuxfwlrq /' ghvw!vuf! /rdg 323 ghvw! 3rs 386+ vuf! 3xvk 7deoh /rjlfdo,qvwuxfwlrqv 0qhprqlf 2shudqgv ,qvwuxfwlrq $1' $vuf! /rjlfdo$1' 25 $vuf! /rjlfdo25 ;25 $vuf! /rjlfdo([foxvlyh25 7deoh 3urjudp&rqwuro,qvwuxfwlrqv 0qhprqlf 2shudqgv ,qvwuxfwlrq &$// $ &doo3urfhgxuh -3 $ -xps 5(7 1rqh 5hwxuq 7deoh 5rwdwhdqg6kliw,qvwuxfwlrqv 0qhprqlf 2shudqgv ,qvwuxfwlrq 5/ ff!$ 5rwdwh/hiw 55 ff!$ 5rwdwh5ljkw 6// ff!$ 6kliw/hiw/rjlfdo 65$ ff!$ 6kliw5ljkw$ulwkphwlf
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ,qvwuxfwlrq2shudqgv to access the operands for the dsp, use the register pointers, data pointers, hardware registers, direct addressing, immediate data and memory. there are nine distinct types of instruction operands. table 59 and table 60 list instructions. 7deoh ,qvwuxfwlrq2shudqg6xppdu\ 6\perolf1dph 6\qwd[ 'hvfulswlrq suhjv! 3qe 5hjlvwhu3rlqwhu guhjv! 'qe 'dwd3rlqwhu kzuhjv! ;<3&65 (;7q$%86 +dugzduh5hjlvwhuv dfflqg! #$ $ffxpxodwru,qgluhfw gluhfw! frqvwh[s! 'luhfw$gguhvv([suhvvlrq olpp! frqvwh[s! /rqj%lw,pphgldwh vlpp! frqvwh[s! 6kruw%lw,pphgldwh9doxh uhjlqg! #3qe #3qe #3qe/rrs #3qe/rrs ,qgluhfw$gguhvvlqjri5$0 phplqg! #'qe #'qe ##3qe ##3qe ##3qe/rrs ##3qe/rrs ,qgluhfw$gguhvvlqjri520 7deoh ,qvwuxfwlrq0qhprqlfv2shudqgv ,qvwuxfwlrq 0qhprqlf2shudqg5hsuhvhqwdwlrq /' 3) /' suhjv!vlpp! /' ;#$ /' kzuhj!dfflqg! /' <&) /' kzuhj!olpp! 68% $##3 68% $phplqg! 25 $#' 25 $phplqg! $' '$) $'' $gluhfw! 386+ ' 386+ guhjv!
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& rtgiu the register pointer mode is used for loading the pointer with the appropriate ram address. this address references the ram location that stores the requested data. the pointer can also be used to store 8-bit data when used as a temporary register. the pointers are connected to the lower 8 bits of the d-bus. instruction 1 loads pointer 2, ram bank0 with the value f2h . tgikpf the register indirect mode is used for indirect access to ram. as noted in instruction 2, the register indirect address method is used to get the operand to multiply it with the accumulator. ftgiu the data-pointer mode is used as an indirect addressing method similar to @p2:0 . the data pointers access the lower 16 bits of each ram bank. instruction 8 uses indirect addressing to push information onto the stack. ogokpf pointer or data registers can be used to access program memory. both are commonly used to reference program memory. instructions 5 and 6 display this addressing method. either pointer is automatically incremented to assist in transferring sequential data. ceekpf another method of indirect addressing is using the accumulator to store the address. instruction 3 describes how to use this method. fktgev the absolute ram address is used in the direct mode. a range between 0 and 511 (000h to 1ffh) is allowed. the accumulator is used in conjunction with this method as a source or destination operand. instruction 7 displays the accumulator as the destination. nkoo this instruction indicates a long immediate load. a 16-bit word can be copied directly from the operand into the specified register or memory. instruction 4 uses this method. ukoo this instruction can only be used for immediate transfer of 8-bit data in the operand to the specified ram pointer. ,qvwuxfwlrq)rupdw the instruction format that specifies to the processor the action to be taken consists of the op code, destination, source, and other special bits. the assembler makes this operation transparent by providing mnemonics. occasionally, the instruction format and development code can assist in debugging. examples to clarify the various instruction formats and explain how specific bit patterns are developed and evaluated are provided below. most instructions require one 16-bit word containing the information necessary for the processor to execute the instruction correctly. this process requires one clock cycle for execution. immediate addressing, immediate operands, jump and call instructions
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& require two 16-bit words (two clock cycles). each instruction type has a unique op code and format to differentiate various instructions. different operations also have unique formats. the variables a, op, b, d, s, cc, am, fm, rp are used in the instruction format to depict bits determined by the active instruction. $'',7,21dqg,1&)rupdwv the op code and format for an instruction differ to allow the processor to differentiate between the instructions. for example, the assition instruction requires that two operands be defined in the instruction. add a, the inc (increment) instruction requires that a condition and modification code be specified. inc a ,1&dqg6//)rupdwv the inc and sll instructions have the same op code with an accumulator modification format. the most recent four bits, the modification code, determine the type of operation the accumulator performs. inc a sll a 6666 2s&rgh 5$0 %dqn &rqglwlrq&rgh 0rglilfdwlrq&rgh 2s&rgh &rqglwlrq&rgh 0rglilfdwlrq&rgh 2s&rgh &rqglwlrq&rgh 0rglilfdwlrq&rgh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ,qvwuxfwlrq%lw&rghv the values in a series of bits in a register form patterns called bit codes . types of bit codes include the following: ? condition codes ? accumulator modification code ? flag modification codes ? source/destination field designators ? register pointer/data pointer the following tables list the options available and their corresponding instructions. &rqglwlrq&rghv table 61 lists the condition codes that are used in accumulator modification, call , and jump instructions. 2s&rgh &rqglwlrq&rgh 0rglilfdwlrq&rgh 7deoh &rqglwlrq&rgh%lwv %lw&rgh 0qhprqlf &rgh9doxh &rqglwlrq &rgh9doxh &rqglwlrq &rgh 00000 ) )dovh 00001 8qxvhg 00010 18 8,lvvhwwr 1rw8vhu=hur 00011 18 8,lvvhwwr 1rw8vhu2qh 00100 1& &lvvhwwr 1r&duu\ 00101 1= =lvvhwwr 1rw=hur1rw (txdo 00110 129 29lvvhwwr 1r2yhuiorz 00111 3/ 1lvvhwwr 3oxv1rw 1hjdwlyh 01xxx 8qxvhg
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $ffxpxodwru0rglilfdwlrq&rghv accumulator modification codes determine the type of modification made to the value in the accumulator. see table 62. condition codes are also used with call, and jump instructions. )odj0rglilfdwlrq&rghv flag modifications initialize or set/reset bits to accommodate interrupts, overflows, and carrys. see table 63. 10000 77uxh 10001 8qxvhg 10010 8 8,lvvhwwr 8vhu=hur 10011 8 8,lvvhwwr 8vhu2qh 10100 & &lvvhwwr &duu\ 10101 = =lvvhwwr =hur(txdo 10110 29 29lvvhwwr 2yhuiorz 10111 0, 1lvvhwwr 0lqxv1hjdwlyh 11xxx 8qxvhg 7deoh $ffxpxodwru0rglilfdwlrq%lwv %lw&rgh 0qhprqlf 2shudwlrq 0000 55 5rwdwh5ljkw 0001 5/ 5rwdwh/hiw 0010 65 6kliw5ljkw 0011 6/ 6kliw/hiw 0100 ,1& ,qfuhphqw 0101 '(& 'hfuhphqw 0110 1(* 1hjdwh 0111 $%6 $evroxwh 7deoh &rqglwlrq&rgh%lwv &rqwlqxhg %lw&rgh 0qhprqlf &rgh9doxh &rqglwlrq &rgh9doxh &rqglwlrq &rgh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6rxufh'hvwlqdwlrq)lhog'hvljqdwruv register pointers and data pointers provide convenient access to data. the pointers are a source or destination field in instructions. specific bit codes are listed in table 64. the register pointer offers optional incrementing or decrementing. this option is specified by the following instruction: ld a, @p2:1+ 7deoh )odj0rglilfdwlrq%lwv %lw&rgh 0qhprqlf 2shudwlrq )odj 9doxh xx10 &&) &ohdu&duu\ & xx11 6&) 6hw&duu\ & x1x0 &,() &ohdu,qwhuuxsw(qdeoh ,( x1x1 6,() 6hw,qwhuuxsw(qdeoh ,( 1xx0 &23) &ohdu2yhuiorz3urwhfwlrq 23 1xx1 623) 6hw2yhuiorz3urwhfwlrq 23 7deoh 5hjlvwhu3rlqwhu'dwd3rlqwhu%lwv %lw&rgh 0qhprqlf 00xx 123 01xx 10xx orrs 11xx orrs xx00 3ru3 xx01 3ru3 xx10 3ru3 0011 'ru' 0111 'ru' 1011 'ru' 1111 &qt&
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& data pointers are automatically incremented when accessing program memory (for example, ld a, @d0:0 ) and do not require an incrementing option. code in xx11 format is designated for a data pointer when source or destination format is used. additional source or destination designators include the other hardware registers provided by the processor. to determine if a data pointer, register pointer or a register is used as a source or destination is discussed in the next section. table 65 lists the bit codes for mnemonic resister names. ,qvwuxfwlrq)rupdw([dpsohv refer to the following examples indicating how bit codes are used in an instruction format. 7deoh 5hjlvwhu%lwv %lw&rgh 0qhprqlf 0000 %xv 0001 ; 0010 < 0011 $ 0100 65 0101 67$&. 0110 3& 0111 5hvhuyhg 1000 (;7 1001 (;7, 1010 (;7 1011 (;7 1100 (;7 1101 (;7 1110 (;7 1111 (;7
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ,qvwuxfwlrq)rupdw $ffxpxodwru0rglilfdwlrq)rupdw 0qvgu 1. the variables a, op, b, d, s, cc, am, fm, rp are used in the instruction format to depict bits determined by the instruction. 2. the general instruction format requires an op code, ram bank bit, destination and source addresses. for example, ld a, @p2:1+ /rdg,qvwuxfwlrq)rupdw the op code ( 0000001 ) provides a unique signature for the ld command. the processor uses this signature to determine the instruction format. the ram bank bit is high (equal to 1) because of the instruction definition b=1 (pn:b) . the destination bit code is 0011 which corresponds to the accumulator. the source 0110 corresponds to the +1 option and p2:0 or p2:1 . the ram bank bit indicates that the processor loaded the accumulator with the operand designated by pointer 2 bank1 ( p2:1 ). source and destination fields can be accessed from the register pointers, data pointers, or registers. the op code specifies the type of source and destination. an op code of 0000101 specifies that the source is an indirect address to program memory ( @@p0.0 or @d0:0 ) and the destination is a register. ,qvwuxfwlrq)rupdw/lvwlqj instruction formats and applicable instructions are listed in table 66 through table 72. rs rs rs rs rs rs rs ff ff ff ff ff dp dp dp dp 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq rs rs rs rs rs rs rs ff ff ff ff ff dp dp dp dp 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 0qvgu 1. several instructions provide various addressing modes to obtain operands; therefore, the same instruction can have several different formats depending on the addressing mode. 2. the variables a, op, b, d, s, ce, am, fm, rp are used in the instruction format to depict bits determined by the specific instruction used. *hqhudo,qvwuxfwlrq)rupdw $ffxpxodwru0rglilfdwlrq)rupdw rs rs rs rs rs rs rs e g g g g v v v v 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh 7deoh *hqhudo,qvwuxfwlrq)rupdw 0qhprqlf 2shudqgv %lw&rgh +h[ $'' $#3 1000001 0 0000 0000 $1' $' 1100110 1 0000 0111 $% &3 $; 0110000 0 0000 0001 /' $3 0000000 0 0011 0111 323 ; 0000000 0 0001 0101 386+ ' 0000001 0 0101 0011 5(7 0000000 0 0110 0101 68% $#' 0010101 1 0000 0111 % ;25 $3 1111001 0 0000 0010 ) rs rs rs rs rs rs rs ff ff ff ff ff dp dp dp dp 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )odj0rglilfdwlrq)rupdw 'luhfw,qwhuqdo$gguhvvlqj)rupdw 7deoh $ffxpxodwru0rglilfdwlrq)rupdw 0qhprqlf 2shudqgv %lw&rgh +h[ 5hsuhvhqwdwlrq $%6 =$ '(& $ ,1& 1=$ 1(* $ 55 18$ 5/ 3/$ 6// &$ 65$ 8$ rs rs rs rs rs rs rs ff ff ff ff ff ip ip ip ip 2s&rgh &rqglwlrq&rgh )odj0rglilfdwlrq 7deoh )odj0rglilfdwlrq)rupdw 0qhprqlf %lw&rgh +h[5hsuhvhqwdwlrq &&) 1001010 00000 0010 &,() 1001010 00000 0100 &23) 1001010 00000 1000 6&) 1001010 00000 0011 6,() 1001010 00000 0101 623) 1001010 00000 1001 rsrsrsrsrsrsrsddddddddd 2s&rgh %lw,qwhuqdo$gguhvv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6kruw,pphgldwh$gguhvvlqj)rupdw /rqj,pphgldwh$gguhvvlqj)rupdw 7deoh 'luhfw,qwhuqdo$gguhvvlqj)rupdw 0qhprqlf 2shudqgv %lw&rgh +h[ 5hsuhvhqwdwlrq $'' $)) 1000011 011111111 )) $1' $ 1010011 011111111 $)) &3 $ 0110011 011111111 )) /' 0000111 000010010 ( rsrsrsrsrsusususdddddddd 2s&rgh 5hjlvwhu 3rlqwhu %lw,pphgldwh$gguhvv'dwd 7deoh 6kruw,pphgldwh$gguhvvlqj)rupdw 0qhprqlf 2shudqgv %lw&rgh +h[ 5hsuhvhqwdwlrq /' 3)$ 00011 101 11111010 ')$ rs rs rs rs rs rs rs e g g g g v v v v 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh ddddddd d dddddddd %lw$gguhvv'dwd
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& jump call )rupdw ,qvwuxfwlrq7lplqj the dsp can be executed with single cycle instruction using the independent data memory and program memory buses offered by the modified harvard architecture and pipeline instruction. this method provides overlapping of instruction fetch and execution cycles. figure 27 illustrates the execution sequence. the first instruction takes two clock cycles to execute; subsequent executions occur in a single cycle. all instruction fetch cycles have the same machine timing regardless of whether external or internal memory is used. because the dsp contains a two-level pipeline, the jump and call instructions do not disrupt the execution process 7deoh /rqj,pphgldwh$gguhvvlqj)rupdw 0qhprqlf 2shudqgv +h[5hsuhvhqwdwlrq $'' $ $1' $$ $$ /' ;))& ))& 386+ && && 68% $ ;25 $$)& ($)& ffffffffffvvvv 2s&rgh &rqglwlrq&rgh 1rw8vhg dddddddddddddddd %lw$gguhvv 7deoh -xps&doo)rupdw 0qhprqlf 2shudqgv +h[5hsuhvhqwdwlrq &$// (1' -3 8(1' '
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& in two-byte instructions, the second byte is being fetched while the first byte is executing. because the processor knows that the instruction is a jump or call , the second byte is transferred to the program counter and the correct address is fetched into the pipeline. there is no disruption or pipeline flushing. the pipeline flow is affected when the program counter is the destination for a load. because the load ( ld ) instruction is a single word instruction, the next instruction is fetched during load execution. to compensate for the instruction in the pipeline, that instruction is executed as a nop . )ljxuh 3lsholqh([hfxwlrq ,qvwuxfwlrq2s&rghv table 73 summarizes essential information about the instruction set. 7deoh ,qvwuxfwlrq2s&rghv ,qvw 'hvfulswlrq 2s&rgh 6\qrsvlv 2shudqgv :rugv &\fohv ([dpsohv $%6 $evroxwh9doxh 1001000 $%6>ff!@vuf! ff!$ $%61&$ 1001000 $ $%6$ $'' $gglwlrq 1001001 $''ghvw! vuf! $suhjv! $''$3 1000001 $guhjv! $''$' 1000100 $olpp! $''$ 1000101 $phplqg! $''$ ##3 1000011 $gluhfw! $''$) 1000001 $uhjlqg! $''$#3 1000000 $kzuhjv! $''$; )hwfk )hwfk ([hfxwh ([hfxwh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $1' %lwzlvh$1' 1011001 $1'ghvw! vuf! $suhjv! $1'$3 1010001 $guhjv! $1'$' 1010100 $olpp! $1'$ 1010101 $phplqg! $1'$##3 1010001 $gluhfw! $1'$& 1010001 $uhjlqg! $1'$ #/223 1010000 $kzuhjv! $1'$(;7 &$// 6xeurxwlqh&doo 0010100 &$// ff!dgguhvv! ff!gluhfw! &$//vxe 0010100 gluhfw! &$//=vxe &&) &ohdu&duu\)odj 1001010 &&) 1rqh &&) &,() &ohdu&duu\)odj 1001010 &,() 1rqh &,() &23) &ohdu23)odj 1001010 &23) 1rqh &23) &3 &rpsdulvrq &3vuf!vuf! 0111001 $suhjv! &3$3 0110001 $guhjv! &3$' 0110101 $phplqg! &3$##3 0110011 $gluhfw! &3$)) 0110001 $uhjlqg! &3$#3 0110000 $kzuhjv! &3$67$&. 0110100 $,lpp! &3$))&) '(& 'hfuhphqw 1001000 '(&>ff!@ghvw! ff!$ '(&1=$ 1001000 $'(&$ ,1& ,qfuhphqw 1001000 ,1&>ff!@ghvw! ff!$ ,1&3/$ 1001000 $ ,1&$ -3 -xps 0100110 -3>ff!@ dgguhvv! ff!gluhfw! -31,(/deho 0100110 gluhfw! -3/deho 7deoh ,qvwuxfwlrq2s&rghv &rqwlqxhg ,qvw 'hvfulswlrq 2s&rgh 6\qrsvlv 2shudqgv :rugv &\fohv ([dpsohv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& /' /rdg'hvwlqdwlrq zlwk6rxufh 0000000 /'ghvw!vuf! $kzuhjv! /'$; 0000001 $guhjv! /'$' 0001001 $suhjv! /'$3 0000001 $uhjlqg! /'$#3 0000101 $phplqg! phplqg! /'$#' 0000011 $gluhfw! /'$ 0000111 gluhfw!$ /'$ 0000100 guhjv! kzuhjv! /''(;7 0001100 suhjv! vlpp! /'3)$ 0001010 suhjv! kzuhjv! /'3(;7 0000110 uhjlqg! olpp! /'#3 0000010 uhjlqg! kzuhjv! /'#30; 0001001 kzuhjv! suhjv! /'<3 0000001 kzuhjv! guhjv! /'65' 0000100 kzuhjv! olpp! /'3& 0100101 kzuhjv! dfflqg! /';#$ 0000101 kzuhjv! phplqg! /'<' 0000001 kzuhjv! uhjlqg! /'$ #3/223 0000000 kzuhjv! kzuhjv! /';(;7 :khqghvw!lvkzuhjv!ghvw!fdqqrweh3 :khqghvw!lvkzuhjv!dqgvuf!lvkzuhjv! ghvw!fdqqrweh(;7qlivuf!lv(;7qghvw! fdqqrweh;livuf!lv;ghvw!fdqqrweh65li vuf!lv65 :khqvuf!lvdfflqg!ghvw!fdqqrweh$ 7deoh ,qvwuxfwlrq2s&rghv &rqwlqxhg ,qvw 'hvfulswlrq 2s&rgh 6\qrsvlv 2shudqgv :rugv &\fohv ([dpsohv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 1(* 1hjdwh 1001000 1(*ff!$ ff!$ 1(*1=$ 1001000 $1(*$ 123 1r2shudwlrq 0000000 123 1rqh 123 25 %lwzlvh25 25ghvw!vuf! 1101001 $suhjv! 25$3 1100001 $guhjv! 25$' 1100100 $olpp! 25$ 1100101 $phplqg! 25 $##3 1100011 $gluhfw! 25$& 1100001 $uhjlqg! 25$ #3/223 1100000 $kzuhjv! 25$(;7 323 3rsd9doxhiurp wkh6wdfn 0001010 323ghvw! suhjv! 3233 0000100 uhjv! 323' 0000010 uhjlqg! 323#3 0000000 kzuhjv! 323$ 386+ 3xvkd9doxh rqwrwkh6wdfn 0001001 386+vuf! suhjv! 386+3 0000001 guhjv! 386+' 0000001 uhjlqg! 386+#3 0000000 kzuhjv! 386+%86 0000100 olpp! 386+ 0100101 dfflqg! 386+#$ 0000101 phplqg! 386+##3 5(7 5hwxuqiurp 6xeurxwlqh 0000000 5(7 1rqh 5(7 5/ 5rwdwh/hiw 1001000 5/ff!$ ff!$ 5/1=$ 1001000 $5/$ 55 5rwdwh5ljkw 1001000 55ff!$ ff!$ 55&$ 1001000 $ 55$ 7deoh ,qvwuxfwlrq2s&rghv &rqwlqxhg ,qvw 'hvfulswlrq 2s&rgh 6\qrsvlv 2shudqgv :rugv &\fohv ([dpsohv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ,qvwuxfwlrq'hvfulswlrqv the dsp instruction set consists of 30 basic instructions, optimized for high-code density and reduced execution time. single-cycle instruction execution is possible because of the pipeline and other architectural features. table 74 contains a description for each instruction. 6&) 6hw&)odj 1001010 6&) 1rqh 6&) 6,() 6hw,()odj 1001010 6,() 1rqh 6,() 6// 6kliw/hiw/rjlfdo 1001000 6// >ff!@$ 6//1=$ 1001000 $6//$ 623) 6hw23)odj 1001010 623) 1rqh 623) 65$ 6kliw5ljkw 1001000 65$ff!$ ff!$ 65$1=$ $ulwkphwlf 1001000 $65$$ 68% 6xewudfw 0011001 68%ghvw! vuf! $suhjv! 68%$3 0010011 $guhjv! 68%$' 0010100 $olpp! 68%$&& 0010101 $phplqg! 68%$#' 0010011 $gluhfw! 68%$ 0010001 $uhjlqg! 68%$ #3/223 0010000 $kzuhjv! 68%$67$&. ;25 %lwzlvh([foxvlyh 25 ;25ghvw!vuf! 1111001 $suhjv! ;25$3 1110001 $guhjv! ;25$' 1110100 $olpp! ;25$ 1110001 $phplqg! ;25$#3 1110011 $gluhfw! ;25$) 1110001 $uhjlqg! ;25$#3 1110000 $kzuhjv! ;25$%86 7deoh ,qvwuxfwlrq2s&rghv &rqwlqxhg ,qvw 'hvfulswlrq 2s&rgh 6\qrsvlv 2shudqgv :rugv &\fohv ([dpsohv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 0qvg each assembly instruction includes an example for each addressing mode available for the specific instruction. the mnemonics listed in table 75 are used in the instruction format. 7deoh ,qvwuxfwlrq'hvfulswlrqv 0qhprqlf 0qhprqlf([sdqvlrq ,qvwuxfwlrq2shudqgv /lvwvwkhw\shvridgguhvvlqjphwkrgvirudvshflilf lqvwuxfwlrq abs a or abs , a ,qvwuxfwlrq)rupdw 'lvsod\vlqvwuxfwlrqirupdwiruuhjlvwhulqgluhfwdgguhvvlqj 2shudwlrq 'lvsod\vrshudwlrqvhtxhqfh $iihfwhg)odjv /lvwviodjvdiihfwhge\rshudwlrq 'hvfulswlrq 'hvfulehvwkhlqvwuxfwlrqrshudwlrq ([dpsohv $vlpsohh[dpsohglvsod\vwkhlqvwuxfwlrqrshudwlrqdqg krzwkhuhjlvwhuvduhdiihfwhg7khh[dpsohlqfoxghv lqlwldol]dwlrqlqvwuxfwlrqdqguhvxow$ovrlqfoxghvf\fohv dqglqvwuxfwlrqohqjwk 7deoh ,qvwuxfwlrq)rupdw0qhprqlfv 0qhprqlf 'hvfulswlrq 0qhprqlf 'hvfulswlrq $ $gguhvv ghvw 'hvwlqdwlrq9doxh dp $ffxpxodwru0rglilfdwlrq ip )odj0rglilfdwlrq e 5$0%dqn rs 2s&rgh ff &rqglwlrq&rgh us 5hjlvwhu3rlqwhu frqvwh[s &rqvwdqw([suhvvlrq v 6rxufh$gguhvv g 'hvwlqdwlrq$gguhvv vuf 6rxufh9doxh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $%6 $evroxwh9doxh $%6 ,qvwuxfwlrq:rug 6\qwd[ abs , a abs a 2shudwlrq if acc < 0 then -(acc) -> acc flags: n : set if the accumulator has 800000h (see below). 'hvfulswlrq if the contents of the accumulator are determined to be less then 0 (a negative number), the absolute value of the accumulator is calculated (accumulator replaced by its two's complement value). using the condition code provides an additional method to evaluate a status flag before the absolute value of the accumulator is calculated. 0qvg if the accumulator contains 800000h , the abs a instruction stores the value of the two's complement at address 800000h and sets the overflow and negative status bits. there is no overflow protection. ([dpsoh abs a initialization: accumulator contains ffeb00h sr contains 0000h instruction: abs a result: accumulator contains 001500h sr contains 1000h this example uses one word of memory and executes in one machine cycle. because the value in the accumulator is less then zero, the two's complement is performed and the result is placed in the accumulator abs(ffebh)=001500h . the carry bit is set. ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh abs , a initialization: accumulator contains 456400h instruction: abs mi, a result: accumulator contains 456400h this example uses one word of memory and executes in one machine cycle. the condition code (negative bit) is not set because the accumulator value is positive; therefore, the instruction is not executed.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $'' $gglwlrq $'' ,qvwuxfwlrq:rug 6\qwd[ add a, add a, add a, add a, add a, add a, add a, 2shudwlrq acc + -> acc flags: c set if carry from the most significant bit is found. n : set if result in the accumulator is negative. z : set if result is 0. ov : set if addition exceeds upper ( fffffh ) or lower ( 800000h ) limit of the accumulator. 'hvfulswlrq the addressed data memory operand is added to the accumulator. the result is loaded into the accumulator. 0qvg the lower eight bits of the accumulator are unchanged while the add instruction is executed. ([dpsoh add a, e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: accumulator contains 123456h p0:0 contains 4dh ram bank1: 4dh contains 8746h instruction: a dd a, @p0:0 result: a contains 997a56h @p0:0 contains 746h this example uses one word of memory and executes in one machine cycle. the pointer p0:0 contains the ram register location ( 4dh ). the contents of ram register 4dh are added to the accumulator to obtain the sum ( 874600h + 123456h = 997a56h ). the sum is contained in the accumulator and the pointer is left unchanged. the direct addressing equivalent is add a, %4d or add a, 77 ( 4dh = 77 decimal). ([dpsoh add a, initialization: accumulator contains 123400h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 2 47ahcontains 0c12h instruction: add a, @@p0:0 result: a contains le4600h p0:0 contains 21h ram bank0: 21h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location ( 21h ). the contents of this register have a rom address. this address refers to the rom data placed in the specified accumulator by an and instruction 123400h + 0c1200h = 1e4600h . when memory indirect addressing is used, the rom address is automatically incremented. to provide a convenient method of accessing sequential data. using add a, @@p0:0+ performs the same operation and also increments the p0:0 content to 22h . ([dpsoh add a, initialization: accumulator contains 123400h instruction: add a, #%0c12 result: a contains le4600h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& this example uses two words of memory and executes in two machine cycles. the immediate operand 0c12h is added to the accumulator to obtain the sum 123400h + 0c1200h = 1e4600h . ([dpsoh add a, initialization: accumulator contains 23400h register x contains 0c12h instruction: add a, x result: a contains 1e4600h this example uses one word of memory and executes in one machine cycle. the contents of register x are added to the accumulator to obtain the sum. 123400h + 0c1200h = 1e4600h . all hardware registers can transfer from . ([dpsoh add a, initialization: accumulator contains 123400h ram bank0: f3h contains 0c12h instruction: add a,%f3 result: a contains 1e4600h this example uses one word of memory and executes in one machine cycle. register f3h is added to the accumulator to obtain the sum. 123400h + 0c1200h = 1e4600h . an equivalent instruction is add a, 243 ( f3h = 243 decimal ). ([dpsoh add a, initialization: accumulator contains 123400h p0:0 contains 56h instruction: add a, p0:0 result: accumulator contains 128a00h this example uses one word of memory and executes in one machine cycle. the contents of the pointer register p0:0 is added to the accumulator. 123400h + 005600h = 128a00h . the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16-bits of the p-bus. this causes the pointer register operand to become 005600h before being added to the accumulator.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh add a, initialization: accumulator contains 123400h d0: 1 contains 8746h instruction: adda,d0:1 result: a contains 997a00h d0: 1 contains 8746h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d0:1 are added to the accumulator. the sum is contained in the accumulator and the pointer is left unchanged. the data pointer contains 8746h .
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $1' %,7:,6($1' $1' ,qvwuxfwlrq:rug 6\qwd[ and a, and a, and a, and a, and a, and a, and a, and a, 2shudwlrq . and. > flags: n : set if accumulator result is less than 0. z : set if accumulator result is 0 . 'hvfulswlrq data is stored in the specified accumulator by an and instruction. the lower eight bits of the accumulator are cleared when this instruction is executed. ([dpsoh and a, initialization: accumulator contains 123456h p0a contains 45h ram bank1: 45h contains 8746h instruction: and a, @p0:1 e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& result: accumulator contains 020400h this example uses one word of memory and executes in one machine cycle. the data in ram bank1, referenced by ram pointer 0, is stored in the specified accumulator using an and instruction 123456h.and.874600h = 020400h. ([dpsoh and a, initialization: accumulator contains 123400h p0:0 contains 45h ram bank0: 45h contains 047ah rom address: 04 7ah contains 8746h instruction: and a, @@p0:0 result: a contains 020400h p0:0 contains 45h ram bank0: 45h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location ( 45h ). the contents of this register has a rom address. this address refers to the rom data that is placed in the specified accumulator by an and instruction 123400h.and.874600h = 020400h . with memory-indirect addressing, the rom address is automatically incremented. this provides a convenient method to access sequential data. using and a, @@p0:0+ performs the same operation and also increments the p0:0 content to 46h . ([dpsoh and a, initialization: accumulator contains 362400h instruction: and a, #%1234 result: accumulator contains 122400h this example uses two words of memory and executes in two machine cycles. the immediate operand 1234h and an accumulator address are processed with an and instruction to produce the result, 362400h.and.123400h = 122400h . ([dpsoh and a, initialization: accumulator contains 123456h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& instruction: and a, #%1f result: accumulator contains 001400h this example uses one word of memory and executes in one machine cycle. the data in the immediate field and the contents of the accumulator are processed with an and instruction. 123456h.and.001f00h = 001400h . ([dpsoh and a, initialization: accumulator contains 123400h register x contains oc12h instruction: and a, x result: a contains 001000h this example uses one word of memory and executes in one machine cycle. use an and instruction to send the contents of register x to the accumulator to obtain the result 123400h.and.0c1200h = 001000h . all hardware registers can transfer from < hwregs >. ([dpsoh and a, initialization: accumulator contains 123400h ram bank0: f3h contains 0c12h instruction: and a, %f3 result: a contains 001000h this example uses one word of memory and executes in one machine cycle. use an and instruction to send register f3h to the accumulator to obtain the result 123400h and oc1200h = 001000h . an equivalent instruction is and a, 243 ( f3h = 243 decimal). ([dpsoh and a, initialization: accumulator contains 123400h p0:0 contains 56h instruction: and a, p0:0 result: accumulator contains 001400h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& this example uses one word of memory and executes in one machine cycle. use an and instruction to send the contents of the pointer register p0:0 to the accumulator 123400h.and.005600h = 001400h . the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this action changes the pointer register operand to 005600h before being added to the accumulator. ([dpsoh and a, initialization: accumulator contains 123400h d0:1 contains 2645h instruction: and a, 00:0 result: accumulator contains 020400h this example uses one word of memory and executes in one machine cycle. the data register, d0:0 , references the operand 2645h . use an and instruction to send this data register to the accumulator to produce the result 123400h.and.2645h = 020400h.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& &$// 68%5287,1(&$// &$// ,qvwuxfwlrq:rug 6\qwd[ call , call 2shudwlrq pc + 2 > stack 16-bit address > pc flags: none 'hvfulswlrq the current program counter ( pc ) register content is incremented by two and placed on the stack. the address of the specified label in the call instruction is then placed in the pc register. the jump is made to the appropriate subroutine via the pc . the condition code option is used if call is executed. ([dpsoh call cycles: 2 words: 2 initialization: pc contains 1ffbh fft2 subroutine address contains f234h stack level 0 contains 0025h instruction: call fft2 effffffffvvvv 2s&rgh &rqglwlrq&rgh 1rw8vhg dddddddddddddddd %lw$gguhvv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& result: pc contains f234h stack level 0 contains 1ffdh stack level 1 contains 0025h this example uses two words of memory and executes in two machine cycles. the call to the subroutine fft2 places pc+2 ( 1 ffdh ) on the stack. all information currently on the stack is pushed up the stack. the subroutine address is then placed in the pc register. the processor executes the next instruction addressed by the pc , the fft2 subroutine. ([dpsoh call , initialization: pc contains 1ffbh fft2 subroutine address contains f234h stack level 0 contains 0025h uo (user zero bit) contains 1 instruction: call uo, fft2 result: pc = f234h stack level 0 = 1ffdh stack level 1 = 0025h this example uses two words of memory and executes in two machine cycles. the condition code uo is tested by the processor before executing the call instruction. because the uo bit is enabled, the call routine is executed exactly like the example above. the condition code uo is input to the processor that determines if subroutine fft2 is used. another call instruction can determine if another subroutine, fft1 , is used. ([dpsoh call initialization: pc contains 1ffbh fft2 subroutine address contains f234h stack level 0 contains 0025h instruction: call fft2 result: pc contains f234h stack level 0 contains 1ffdh stack level 1 contains 0025h this example uses two words of memory and executes in two machine cycles. the call to the subroutine fft2 places pc+2 ( 1 ffdh ) on the stack. all information currently on
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& the stack is pushed up the stack. the subroutine address is then placed in the pc register. the processor executes the next instruction addressed by the pc , the fft2 subroutine.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& &&) &/($5&$55<)/$* &&) ,qvwuxfwlrq:rug 6\qwd[ ccf 2shudwlrq zero > carry bit flags: c :set to 0 . 'hvfulswlrq the clear carry flag instruction resets the carry flag with a 0 . ([dpsoh ccf initialization: sr contains 3000h instruction: ccf result: sr contains 2000h c contains 0 this example uses one word of memory and executes in one machine cycle. 2s&rgh &rqglwlrq&rgh )odj0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& &,() &/($5,17(55837(1$%/()/$* &,() ,qvwuxfwlrq:rug 6\qwd[ cief 2shudwlrq zero > ie bit flags: ie : set to 0 . 'hvfulswlrq the clear interrupt enable flag instruction sets the ie flag to 0 . ([dpsoh cief initialization: sr contains 3080h instruction: cief result: sr contains 3000h ie contains 0 this example uses one word of memory and executes in one machine cycle. 2s&rgh &rqglwlrq&rgh )odj0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& &23)&/($5 29(5)/2:3527(&7,21)/$* &23&/($5 ,qvwuxfwlrq:rug 6\qwd[ copf 2shudwlrq zero > op bit flags: p :set to 0 . the clear overflow protection flag instruction resets the op flag to 0 . ([dpsoh copf initialization: sr contains 0100h instruction: copf result: sr contains 0000h op contains 0 this example uses one word of memory and executes in one machine cycle. 2s&rgh &rqglwlrq&rgh )odj0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& &3 &203$5,621 &3 ,qvwuxfwlrq:rug 6\qwd[ cp a, cp a, cp a, cp a, cp a, cp a, cp a, cp a, 2shudwlrq a - > set appropriate status bits flags: c : set if carry is required for operation. z : set if operands are equal. ov : set if operation exceeds the low ( 800000h ) or high limit ( 7fffffh ) of accumulator. n : set if result is negative. 'hvfulswlrq the contents of the register specified in the instruction are compared to the contents of the accumulator in 16-bit mode. the register specified is subtracted from the accumulator and the appropriate flags are set. because the registers are 16-bit, a comparison with the 24-bit accumulator requires that the lower eight bits of the accumulator be filled with zeros for accurate comparisons. the instruction does not affect the contents of the accumulator except when the overflow protection bit is set and an overflow occurs after the compare is executed. the accumulator updates with the appropriate low ( 800000h ) or high ( 7fffffh ) limit. e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh cp a, initialization: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5463h instruction: cp a, @p2:1 result: a contains 7a2500h sr contains 1000h this example uses one word of memory and executes in one machine cycle. the operand referenced by p2:1 is subtracted from the accumulator. 7a2500h - 546300h = 25c200h . because the comparison does not yield a 0 , bit 0 is not set. the content of the p2:1 register is appended with eight additional 0 bits. for consistent comparisons, the accumulator must contain zeros in the lower eight bits. 0qvg the accumulator is unaffected by the operation. ([dpsoh cp a, initialization: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5463h rom address: 5463h contains oc12h instruction: cp a, @@p2:1 result: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5464h sr contains 1000h this example uses one word of memory and executes in three machine cycles.the pointer p2:1 contains the ram register location ( a4h ). the contents of this register have a rom address. this address refers to the rom data compared to the accumulator 7a2500h - oc1200h = 6e1300h . because the comparison does not yield a 0 , bit 0 is not set. with memory indirect addressing, the rom address is automatically incremented. using cp a,@@p2:1 + performs the same operation and also increments p2:1 content to a5h . ([dpsoh cp a,
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: a contains 7a2500h instruction: cp a, #%7a25 result: a contains 7a2500h sr contains 3000h this example uses two words of memory and executes in two machine cycles. the immediate operand is compared to the accumulator. because they are equal, the zero flag is set. ([dpsoh cp a, initialization: a contains 7a2500h sr contains 0000h bus contains 7a25h instruction: cp a, bus result: a contains 7a2500h sr contains 3000h this example uses one word of memory and executes in one machine cycle. the < hwreg > operand is subtracted from the accumulator. because the two operands are equal, the zero-status bit is set high . < hwregs > can be compared from all hardware registers. ([dpsoh cp a, initialization: accumulator contains 7a2500h ram bank0 f3h contains 5463h instruction: cp a, %f3 result: a contains 7a2500h sr contains 1000h this example uses one word of memory and executes in one machine cycle. register f3h is compared to the accumulator. 7a2500h - 546300h = 25c200h. an equivalent instruction is cp a,243 ( 173h = 243 decimal). ([dpsoh cp a,
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: accumulator contains 123400h p0:0 contains 56h instruction: cp a, p0:0 result: accumulator contains 123400h sr contains 1000h this example uses one word of memory and executes in one machine cycle. the contents of the pointer register p0:0 are compared to the accumulator. 123400h - 005600h = 11de00h the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this action changes the pointer register operand to 005600h before being compared to the accumulator. ([dpsoh cp a, initialization: a contains 7a2500h d2:1 contains 5463h instruction: cp a, d2:1 result a contains 7a2500h sr contains 1000h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d2:1 are compared to the accumulator. 7a2500h - 546300h = 25c200h.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& '(& '(&5(0(17 '(& ,qvwuxfwlrq:rug 6\qwd[ dec a dec , a 2shudwlrq acc - 1 > acc flags: c : set if carry is required for operation z : set if result is 0 . n : set if decrement results in a value less then 0 . ov : set if upper (7fffffh) or lower (800000h) limits are exceeded. 'hvfulswlrq the accumulator decrements by 1 . a condition code can be used to test for a specific condition before decrementing. ([dpsoh dec a initialization: a contains 7a2500h instruction: dec a result: a contains 7a24ffh this example uses one word of memory and executes in one machine cycle. the value in the accumulator decrements by 1 . ([dpsoh dec , a initialization: a contains 7a2500h ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& instruction: dec mi, a result: a contains 7a2500h this example uses one word of memory and executes in one machine cycle. because the accumulator is not negative, the decrement instruction is not executed.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ,1& ,1&5(0(17 ,1& ,qvwuxfwlrq:rug 6\qwd[ inc , a inc a 2shudwlrq acc + 1 > acc flags: c : set if carry is required for operation. z : set if result is 0 . n : set if results in a value less then 0. ov : set if upper (7fffffh) or lower (800000h) limits are exceeded. 'hvfulswlrq the increment instruction adds one to the accumulator. a condition code can be used to test for a specific condition for an increment to occur. ([dpsoh inc , a initialization: a contains 7a2500h instruction: inc mi, a result: a contains 7a2500h this example uses one word of memory and executes in one machine cycle. because the accumulator is not negative, the increment instruction is not executed. ([dpsoh inc a initialization: a contains 7a2500h ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& instruction: inc a result: a contains 7a2501h this example uses one word of memory and executes in one machine cycle. the value in the accumulator is incremented by 1.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& -3 -803 -3 ,qvwuxfwlrq:rug 6\qwd[ jp , jp 2shudwlrq 16-bit address > pc flags: none 'hvfulswlrq the instruction places the address of the referenced rom location in the program counter ( pc ). because the processor obtains its next instruction address from the pc , the processor jumps to the appropriate location. a condition code can be used to test for a specific condition for a jump to occur. ([dpsoh jp , initialization: routine 1 address contains 1455h pc contains 1343h user 0 input contains 1 instruction: jp nuo, routine 1 result: pc contains 1343h this example uses two words of memory and executes in two machine cycles. because the user 0 input is set high , the condition code is not met. therefore, the jump instruction does not execute. the user 0 input is used to control the flow of the software. ffffffffff 2s&rgh &rqglwlrq&rgh 1rw8vhg d ddddddddddddddd %lw$gguhvv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh jp initialization: routine 1 address contains 1455h pc contains 1343h instruction: jp routine 1 result: pc contains 1455h this example uses two words of memory and executes in two machine cycles. the value in the program counter is replaced by the routine 1 address ( 1455h ).
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& /' /2$' /' ,qvwuxfwlrq:rug 6\qwd[ ld a, ld , a ld , ld a, ld , ld , ld a, ld , ld , ld a, ld , ld , ld a, ld , ld , ld a, ld , < pregs> ld , 2shudwlrq > flags: none e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 'hvfulswlrq the load command provides the ability to transfer data to several different locations in the processor including hardware registers, accumulator, stack, pointers and memory. all transfers across the various internal buses are transparent to the user. 0qvgu 1. a load using the x or y register provides an automatic multiply operation. this means the operand can be obtained from any register location. 2. the p register is a read-only register, therefore the destination of the load cannot be the p register. 3. ld extn , extn is not allowed. 4. a load instruction to the accumulator clears the lower 8 bits of the 24-bit accumulator. ([dpsoh ld a, initialization: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5463h instruction: ld a, @p2:1 result: a contains 546300h this example uses one word of memory and executes in one machine cycle. indirect addressing through the pointer registers provides access to ram data. the data in ram bank 1 , register a4 is transferred to the accumulator. the contents of the p2:1 register are appended with eight additional 0 bits. this is added to verify a correct arithmetic comparison. ([dpsoh ld a, initialization: accumulator contains 123400h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 247ah equals oc1 2h instruction: ld a, @@p0:0
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& result: a contains oc1 200h p0:0 contains 21h ram bank0: 21h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location (21h) . the contents of this register have a rom address. this address refers to the rom data that loads to the accumulator. when memory indirect addressing is used, the rom address is automatically incremented. using ld a, @@p0:0+ has the same result, also incrementing the p0:0 content to 22h . ([dpsoh ld a, cycles: 2 words: 2 initialization: accumulator contains 123400h instruction: ld a, #%2474 result: a contains 247400h this example uses two words of memory and executes in two machine cycles. the immediate operand 2474h loads to the accumulator. ([dpsoh ld a, initialization: accumulator contains 123400h register x contains oc12h instruction: ld a, x result: a contains oc1200h this example uses one word of memory and executes in one machine cycle. the contents of register x are loaded to the accumulator. all hardware registers can transfer from . ([dpsoh ld a, initialization: accumulator contains 123400h ram bank0 f3h contains oc12h instruction: ld a, %f3 result: a contains oc1200h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& this example uses one word of memory and executes in one machine cycle. register f3h is loaded to the accumulator. an equivalent instruction is ld a,243 ( f3h = 243 decimal). ([dpsoh ld a, initialization: accumulator contains 123400h d0: 1 contains 8746h instruction: ld a, d0:1 result: a contains 874600h d0: 1 contains 8746h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d0:1 load to the accumulator. ([dpsoh ld a, initialization: accumulator contains 123400h p0:0 contains 56h instruction: ld a, p0:0 result: accumulator contains 005600h this example uses one word of memory and executes in one machine cycle. the contents of the pointer register p0:0 are loaded to the accumulator. the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this operation causes the pointer register operand to become 005600h before being loaded into the accumulator. ([dpsoh ld , a initialization: accumulator contains 123400h ram bank0: 3ch contains 5678h instruction: ld %3c, a result: accumulator contains 123400h ram bank0: 3ch contains 1234h this example uses one word of memory and executes in one machine cycle. the current value in the accumulator is loaded to the register addressed by the instruction ( 3ch ). an equivalent instruction is ld 60, a . ( 3ch = 60 decimal).
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh ld , initialization: p2:0 contains 2fh ram bank0: 3fh contains 254645h instruction: ld p2:0, #%3f result: p2:0 contains 3fh ram bank0: 3fh contains 254645h this example uses one word of memory and executes in one machine cycle. the immediate data ( 3fh ) is loaded into the pointer register p2:0 . this action provides a convenient method for initializing pointer registers. ([dpsoh ld , initialization: p0: 1 contains 2fh y contains 2376h instruction: ld p0:1, y result: p0: 1 contains 76h y contains 2376h this example uses one word of memory and executes in one machine cycle. the lower 8-bits of the y register are transferred to the pointer register p0:1 . all hardware registers can transfer from . ([dpsoh ld , initialization: p0:1 contains 2fh ram bank0: 2fh contains 2376h instruction: ld @p0:1, #%35b8 result: p0:1 contains 2fh ram bank1: 2fh contains 35b8h this example uses two words of memory and executes in two machine cycles. the immediate operand 35b8h is transferred to the register 2fh of ram bank1. ([dpsoh ld ,
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: p2:0 contains 2fh x register contains 8b87h instruction: ld x,p2:0 result: p2:0 contains 2fh x register contains 002fh this example uses one word of memory and executes in one machine cycle. the contents of the p2:0 pointer ( 2fh ) are loaded into the x register. transfer to < hwreg > is possible to all hardware registers except the read-only p register. ([dpsoh ld , initialization: d2:0 contains 3c87h accumulator contains 8bb722h instruction: ld a,d2:0 result: d2:0 contains 3c87h accumulator contains 3c8700h this example uses one word of memory and executes in one machine cycle. the contents of the d2:0 pointer ( 3c87h ) are loaded into the accumulator. transfer to < hwregs > is possible to all hardware registers except the read-only p register. ([dpsoh ld , initialization: stack0 contains 8b2fh stack1 contains 0000h instruction: ld stack, #%35b8 result: stack0 contains 35b8h stack1 contains 8b2fh this example uses two words of memory and executes in two machine cycles. the immediate data is pushed onto the stack as previous stack data is pushed up the stack. transfer to < hwregs > is possible to all hardware registers except the read-only p register. ([dpsoh ld ,
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: ext7 register contains 8b87h accumulator contains 77b6h rom 77b6h contains 387dh instruction: ld ext7, @a result: ext7 register contains 387dh accumulator contains 77b6h this example uses one word of memory and executes in one machine cycle. the contents of the rom register 77b6h ( 387dh ) are loaded into external register 7 . transfer to < hwregs > is possible to all hardware registers except the read-only p register and the accumulator register. ([dpsoh ld , initialization: y register contains 1234h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 247ah contains 0c12h instruction: lid y, @@p0:0 result: y register contains 0c12h p0:0 contains 21h ram bank0: 21h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location ( 21h ). the contents of this register have a rom address that refers to the rom data that loads to the y register. transfer to < hwregs > is possible to all hardware registers except the read-only p register. when memory indirect addressing is used the rom address is automatically incremented. using ld a,@@p0:0+ performs the same operation and also increments the p0:0 content to 22h . ([dpsoh ld , initialization: x register contains 7a25h p21 contains a4h ram bank1: a4h contains 5463h instruction: ld x, @p2:1
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& result: x register contains 5463h this example uses one word of memory and executes in one machine cycle. indirect addressing through the pointer registers provides access to ram data. the data in ram bank 1, register a4 is transferred to the x register. transfer to < hwreg > is possible to all hardware registers except the read-only p register. ([dpsoh ld , initialization: x register contains 7a25h ext5 register contains 789ah instruction: ld x, ext5 result: x register contains 789ah ext5 register contains 789ah this example uses one word of memory and executes in one machine cycle. the ext5 register contents are transferred to the x register. transfer to < hwregs > is possible to all hardware registers except the read-only p register.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 1(* 1(*$7( 1(* ,qvwuxfwlrq:rug 6\qwd[ neg a neg , a 2shudwlrq -acc > acc flags: n set if result is a negative number. two special cases are: 1. if acc contains 000000 after execution, then n and 0v are cleared, and z and c are set 2. if acc contains 800000 after execution, then n and 0v are set; and z and c are cleared. the accumulator is replaced with a negative of the current value. to achieve this state, the two's complement is performed. ([dpsoh neg a initialization: a contains 003654h instruction: neg a result: a contains ffc9ach this example uses one word of memory and executes in one machine cycle. ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh neg , a initialization: a contains 000111h carry bit contains 1 instruction: neg c, a result: a contains fffeefh this example uses one word of memory and executes in one machine cycle.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 123 1223(5$7,21 123 ,qvwuxfwlrq:rug 6\qwd[ nop 2shudwlrq pc+ 1> pc flags: none 'hvfulswlrq the nop instruction causes the processor to continue operation for one cycle without affecting previous registers and i/0.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 25 %,7:,6(25 25 ,qvwuxfwlrq:rug 6\qwd[ or a, or a, or a, or a, or a, or a, or a, or a, 2shudwlrq acc .or. source > acc flags: n set if result in accumulator is negative. z set if result is 0 . 'hvfulswlrq the accumulator performs an or instruction on the contents of the specified register. the upper 16 bits of the accumulator are used. the result is placed in the accumulator. the or instruction is frequently used to compare specific bits to assist in program control. 0qvg the lower eight bits of the accumulator are unchanged after execution of the or instruction. ([dpsoh or a, e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: accumulator contains 3264a0h p0:0 contains e2h ram bank0: e2h contains 1126h instruction: or a, @p0:0 result: a contains 336600h this example uses one word of memory and executes in one machine cycle. use an or instruction to reference the operand p0:0 with the upper 16 bits of the accumulator. the result is stored in the accumulator. 3264a0h or. 1126a0h = 3366a0h. ([dpsoh or a, initialization: a contains 3264a0h p2:11 contains a4h ram bank 1: a4h contains 5463h rom address: 5463h contains 1126h instruction: or a, @@p2:1 result a contains 3366a0h p2:1 contains a4h ram bank0: a4h contains 5464h sr contains 0000h this example uses one word of memory and executes in three machine cycles. the pointer p2:1 contains the ram register location ( a4h ). the contents of this register have a rom address. this address refers to the rom data that is compared to the accumulator. 3264a0h.or.112600h = 3366a0h . with memory indirect addressing, the rom address is automatically incremented. using ora,@@p0:0+ performs the same operation and also increments the p0:0 content to a5h . ([dpsoh or a, initialization: a contains 3264a0h instruction: or a, #%1126 result: a contains 3366a0h sr contains 0000h this example uses two words of memory and executes in two machine cycles. the accumulator performs an or instruction on the immediate data.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 323 3239$/8()52067$&. 323 ,qvwuxfwlrq:rug 6\qwd[ pop pop pop pop 2shudwlrq stack 0 > stack n > stack n-1 flags: none 'hvfulswlrq the current value of the stack is copied to the specified register. because the stack is a last-in, first-out (lifo) hard-wired architecture, the copy and shift of data remaining in the stack are all performed in a single cycle. the pop instruction provides the ability to control information sent to the stack, making it possible to expand the stack using software. ([dpsoh pop initialization: stack 1 contains 0426h stack 0 contains 0c06h p0:0 contains 24h instruction: pop p0:0 result stack 0 contains 0426h p0:0 contains 06h rsrsrsrsrsrsrse ggggvvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& this example uses one word of memory and executes in one machine cycle. the destination of stack 0 (item on top of stack) is p0:0 . the 8-lsb s of the data in stack 0 are loaded into p0:0 . at transfer, stack 1 is automatically moved to stack 0 . ([dpsoh pop initialization: stack 1 contains 0426h stack 0 contains 0c06h d0:0 contains 7676h instruction: pop d0:0 result: stack 0 contains 0426h d0:0 contains 0c06h this example uses one word of memory and executes in one machine cycle. the destination of the stack 0 (item on top of stack) is given by d0:0 . when transferred, stack 1 is automatically moved to stack 0 . ([dpsoh pop initialization: stack 1 contains 0426h stack 0 contains 0c06h p0:0 contains 24h ram bank0: 24h contains 42a4h instruction: pop @p0:0 result stack 0 contains 0426h ram bank0: 24h contains 0c06h this example uses one word of memory and executes in one machine cycle. the destination of the stack 0 (item on top of stack) is given by p0:0 . 24h is the register location in ram bank0 to which the stack item is transferred. at transfer, stack 1 is automatically moved to stack 0. ([dpsoh pop
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: stack 1 contains 0426h stack 0 contains 0c06h x register contains 089ch instruction: pop x result: stack 0 contains 0426h x register contains 0c06h this example uses one word of memory and executes in one machine cycle. the destination of the stack 0 (item on top of stack) is given by the x register. at transfer, stack 1 is automatically moved to stack 0. transfer to < hwregs > is possible to all hardware registers except the read-only p register.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 386+ 386+9$/8(217267$&. 386+ ,qvwuxfwlrq:rug 6\qwd[ push push push push push push push push 2shudwlrq > stack stack n > stack n+ 1 flags: none 'hvfulswlrq the contents of the specified register are placed on the stack. because the stack is a last-in, first-out (lifo) hard-wired architecture, the placement and shifting of current stack data is performed in a single cycle. the push instruction provides the ability to control information sent to the stack, making it possible to expand the stack through software. ([dpsoh push e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: stack 0 contains 0c06h p1:1 contains a4h instruction: push p1:1 result stack 1 contains 0c06h stack 0 contains 00a4h this example uses one word of memory and executes in one machine cycle. the pointer p1:1 contains the 8-bit value a4h . the 16-bit value, 00a4h , is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. ([dpsoh push initialization: stack 1 contains 0426h stack 0 contains 0c06h d1:1 contains 42a4h instruction: push d1:1 result stack 1 contains 0c06h stack 0 contains 42a4h this example uses one word of memory and executes in one machine cycle. the pointer d1:1 is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. ([dpsoh push initialization: stack 1 contains 0426h stack 0 contains 0c06h ram bank0: 24h contains 42a4h p1:1 contains a4h ram bank1: a4h contains 5463h rom address 5463h contains 1126h instruction: push @@p1:1 result: stack 1 contains 0c06h stack 0 contains 1126h ram bank1: a4h contains 5464h this example uses one word of memory and executes in three machine cycles. when memory indirect addressing is used, the rom address is automatically incremented.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& using or a,@@p0:0+ performs the same operation and also increments the p0:0 content to a5h . ([dpsoh push initialization: stack 1 contains 0426h stack 0 contains 0c06h accumulator contains 42a4h rom addres s 42a4h contains 4c45h instruction: push @a result stack 1 contains 0c06h stack 0 contains 4c45h this example uses one word of memory and executes in one machine cycle. indirect addressing with the accumulator points to the rom memory ( 42a4h ) the data in this location is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. ([dpsoh push initialization: stack 1 contains 0426h stack 0 contains 0c06h p1:1 contains a4h ram bank1: a4h contains 42a4h instruction: push @p1:1 result: stack 1 contains 0c06h stack 0 contains 42a4h ram bank1: a4h contains 42a4h this example uses one word of memory and executes in one machine cycle. the pointer p1:1 contains the ram register location ( a4h ). the data at this location is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. ([dpsoh push initialization: stack 1 contains 0426h stack 0 contains 0c06h x register contains 42a4h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& instruction: push x result: stack 1 contains 0c06h stack 0 contains 42a4h this example uses one word of memory and executes in one machine cycle. the data in the x register is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1 . transfer from < hwregs > is possible from all hardware registers. ([dpsoh push initialization: stack 1 contains 0426h stack 0 contains 0c06h ram bank0: 24h contains 42a4h instruction: push %24 result: stack 1 contains 0c06h stack 0 contains 42a4h this example uses one word of memory and executes in one machine cycle. the instruction ( 24h ) provides the direct register address. the value contained in this register is pushed onto the stack ( 42a4h ). at transfer, stack 0 is automatically moved to stack 1. ([dpsoh push initialization: stack 1 contains 0426h stack 0 contains 0c06h instruction: push #%5757 result: stack 1 contains 0c06h stack 0 contains 5757h this example uses two words of memory and executes in two machine cycles. the immediate operand 5757h is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1 .
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 5(7 5(7851)52068%5287,1( 5(7 ,qvwuxfwlrq:rug 6\qwd[ ret 2shudwlrq stack 0 > pc stack n > stack n-1 flags: none 'hvfulswlrq the current stack information is popped from the stack and placed in the program counter (pc) register. the jump is made from the subroutine via the pc. ([dpsoh ret initialization: stack 1 contains 0624 stack 0 contains 0401 pc contains 06df instruction: ret result: stack 0 contains 0624 pc contains 0401h this example uses one word of memory and executes in one machine cycle. 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 5/ 527$7(/()7 5/ ,qvwuxfwlrq:rug 6\qwd[ rl a rl ,a 2shudwlrq c <= 23 ------------ < ---------- 8 <= c flags: n set if result of accumulator is negative z set if result is zero. c set if msb is set before rotate. 'hvfulswlrq the upper 16 bits of the accumulator are rotated left through the carry bit. the lower 8 bits remain unchanged while the resultant lsb, bit 0, is placed with the value 0 (see the accumulator section). ([dpsoh rl a initialization: a contains 226a84h carry bit contains 1 instruction: rl a result: a contains 44d584h carry bit contains 0 this example uses one word of memory and executes in one machine cycle. the upper 16 bits ( 226ah ) are shifted left through the carry bit to produce 44d5h . the lower 8 bits ( 84h ) remain unchanged. ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh rl , a initialization: a contains 226a84h carry bit contains 0, z=0 instruction: rl z, a result: a contains 226a84h this example uses one word of memory and executes in one machine cycle. the condition code 0 is not set; therefore, the instruction is not executed.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 55 527$7(5,*+7 55 ,qvwuxfwlrq:rug 6\qwd[ rr a rr , a 2shudwlrq c =>23 ---- > 8 = => 7 - -> -- 0 > discarded flags: n set if result of accumulator is negative. z set if result is 0. c set if lsb is set before rotate. 'hvfulswlrq the upper 16 bits of acc are rotated right through the carry bit. the msb of the lower 8 bits also obtains the data shifted from the lsb of upper 16 bits. the lower 8 bits are shifted right with the lsb being discarded. ([dpsoh rr a initialization: a contains 226a84h carry bit contains 0 instruction: rr a result: a contains 113542h this example uses one word of memory and executes in one machine cycle. the upper 16 bits ( 226ah ) are shifted right through the carry bit to produce 1135h . the lower 8 bits ( 84h ) are shifted right to provide 42h . ([dpsoh rr , a ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: a contains 226a84h carry bit contains 0, z=0 instruction: rr z, a result: a contains 226a84h this example uses one word of memory and executes in one machine cycle. the condition code 0 is not set; therefore, the instruction is not executed.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6&) 6(7&$55<)/$* 6&) ,qvwuxfwlrq:rug 6\qwd[ scf 2shudwlrq 1 > carry bit flags: c set to 1. 'hvfulswlrq the set carry flag instruction places a one in the carry bit (bit 12 of the status register). ([dpsoh scf initialization: sr contains 2000h instruction: scf result: sr contains 3000h c contains 1 this example uses one word of memory and executes in one machine cycle. rs rs rs rs rs rs rs ff ff ff ff ff ip ip ip ip 2s&rgh &rqglwlrq&rgh )odj0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6,() 6(7,17(55837(1$%/()/$* 6,() ,qvwuxfwlrq:rug 6\qwd[ sief 2shudwlrq 1 > ie bit flags: none 'hvfulswlrq the instruction places a 1 in bit 7 of the status register and is used to enable interrupts. ([dpsoh sief initialization: sr contains 3000h instruction: sief result: sr contains 3080h ie contains 1 this example uses one word of memory and executes in one machine cycle. ffffffffff 2s&rgh &rqglwlrq&rgh )odj0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6// 6+,)7/()7/2*,&$/ 6// ,qvwuxfwlrq:rug 6\qwd[ sll a sll , a 2shudwlrq discarded < c <= 23 - - - - < - - - -0 <= 0 flags: n set if result of accumulator is negative (bit 23 set to 1 ). z set if result is 0. c set if msb is set before shift. 'hvfulswlrq all 24 bits of the accumulator are shifted left through the carry bit. the msb, bit 23, passes through the carry bit before being discarded. the lsb, bit 0 , is filled with a zero. subsequent shifts cause additional zeroes to be shifted in. ([dpsoh sll a initialization: a contains 226a84h carry bit contains 0 instruction: sll a result: a contains 226a84h this example uses one word of memory and executes in one machine cycle. all 24 bits of the accumulator are shifted left through the carry bit, producing the result 44d508h . ([dpsoh sll , a ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: a contains 226a84h carry bit contains 0 instruction: sll mi, a result: a contains 226a84h this example uses one word of memory and executes in one machine cycle. the condition code n is not set, and the instruction is not executed.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 623) 6(729(5)/2:3527(&7,21)/$* 623) ,qvwuxfwlrq:rug 6\qwd[ sopf 2shudwlrq 1 > op bit flags: none 'hvfulswlrq the set overflow protection flag instruction places a one in bit 8 of the status register. if an alu operation exceeds the limits of the processor, the overflow protection sets the overflow flag ( ov) and holds the limit value in the accumulator. ([dpsoh sopf initialization: sr contains 0000h instruction: sopf result: sr contains 0100h op contains 1 this example uses one word of memory and executes in one machine cycle. 2s&rgh &rqglwlrq&rgh )odj0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 65$ 6+,)75,*+7$5,7+0(7,& 65$ ,qvwuxfwlrq:rug 6\qwd[ sra a sra , a 2shudwlrq 23 => 23 --- > ---- 0 => discarded flags: n set if result of accumulator is negative. z set if result is 0. c set if lsb is set before the shift. 'hvfulswlrq all 24 bits of the accumulator are shifted right with sign extension through the carry bit. the msb, bit 23 , is replicated in vacated bits. the lsb, bit 0 , is passed through the carry before it is discarded. ([dpsoh sra a initialization: a contains 226a84h carry bit contains 0 instruction: sra a result: a contains 113542h carry bit contains 0 this example uses one word of memory and executes in one machine cycle. all 24 bits of the accumulator are shifted right. the msb, bit 23 , is copied into bit 22. the lsb, bit 0 , is discarded. ffffffffff 2s&rgh &rqglwlrq&rgh $&&0rglilfdwlrq
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh sra , a initialization: a contains 226a84h carry bit contains 0, n=0 instruction: sra a result: a contains 113542h carry bit contains 0 this example uses one word of memory and executes in one machine cycle. the condition code is set; therefore, the instruction is executed. the initialization of the accumulator sets the pl ( nn ) condition code.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 68% 68%75$&7 68% ,qvwuxfwlrq:rug 6\qwd[ sub a, sub a, sub a, sub a, sub a, sub a, sub a, sub a, 2shudwlrq acc C (source) > acc flags: c set if a carry from the most significant bit is performed. n set if the result in the accumulator is negative. z set if the result is 0 . ov set if the addition exceeds the upper ( 7fffffh ) or lower ( 800000h ) limit of the accumulator. 'hvfulswlrq the addressed data memory operand is subtracted from the accumulator. the result is loaded into the accumulator. the lower eight bits of the accumulator are cleared by the execution of the subtract instruction. ([dpsoh sub a, e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: accumulator contains 874600h p0: 1 contains 45h ram bank1: 45h contains 1234h instruction: sub a, @p0:1 result: a contains 751200h @p0:1 contains 1234h this example uses one word of memory and executes in one machine cycle. the contents of the register pointed by p0:1 are subtracted from the accumulator. the difference is contained in the accumulator and the pointer is left unchanged. the register pointer contains 45h . because the pointer references ram bank1, the absolute register is 145h ( 325 ). therefore, the contents of register 145h are subtracted from the accumulator. 874600h - 123400h = 751200h . the direct addressing equivalent is sub a,%145 or sub a,325. ([dpsoh sub a, initialization: accumulator contains 874600h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 247ah contains 1234h instruction: sub a, @@p0:0+ result: a contains 751200h p0:0 contains 22h ram bank0: 21 h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer is used for memory indirect addressing. the pointer contains the address of the ram (address 247ah ). the ram contains the address of the requested rom data ( data 247ah ). this operand is subtracted from the accumulator. 874600h - 123400h = 751200h . ([dpsoh sub a, initialization: accumulator contains 874600h instruction: sub a, #%1234 result: accumulator contains 751200h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& this example uses two words of memory and executes in two machine cycles. the immediate operand 8746h is subtracted from the accumulator. 874600h - 123400h = 751200h. ([dpsoh sub a, initialization: accumulator contains 874600h register x contains 1234h instruction: sub a, x result: a contains 751200h this example uses one word of memory and executes in one machine cycle. the contents of register x are subtracted from the accumulator. 874600h - 123400h = 751200h . transfer from < hwregs > is possible from all hardware registers. ([dpsoh sub a, initialization: accumulator contains 874600h ram bank0: f3h contains 1234h instruction: sub a, %f3 result: a contains 751200h this example uses one word of memory and executes in one machine cycle. the contents of register f3h are subtracted from the accumulator. 874600h - 123400h = 751200h . an equivalent instruction is sub a, 243 ( f3h = 243 decimal). ([dpsoh sub a, initialization: accumulator contains 874600h d0: 1 contains 1234h instruction: sub a, d0:1 result: a contains 751200h d0:1 contains 1234h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d0:1 are subtracted from the accumulator. the difference is contained in the accumulator and the pointer is left unchanged.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ([dpsoh sub a, initialization: accumulator contains 874600h p0:0 contains 56h instruction: sub a, p0:0 result: accumulator contains 86f000h this example uses one word of memory and executes in one machine cycle. the contents of pointer register p0:0 are subtracted from the accumulator. 874600h - 005600h = 86f000h. the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this causes the pointer register operand to become 005600h before it is subtracted from the accumulator.
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& ;25 %,7:,6((;&/86,9(25 ;25 ,qvwuxfwlrq:rug 6\qwd[ xor a, xor a, xor a, xor a, xor a, xor a, xor a, xor a, 2shudwlrq a.xor. > a flags: c set if carry from the most significant bit is performed. n set if result in the accumulator is negative. z set if result is 0 . ov set if operation exceeds upper ( 7fffffh ) or lower ( 800000h ) limit of accumulator. 'hvfulswlrq with the accumulator, perform an xor instruction on the addressed data memory operand. the result loads into the accumulator. the lower eight bits of the accumulator are cleared by the xor instruction. ([dpsoh xor a, e vvvv 2s&rgh 5$0 %dqn 'hvwlqdwlrq 6rxufh
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& initialization: accumulator contains 005600h p0:0 contains 00h ram bank0: 00h contains 1234h instruction: xor a, @p0:0 result: a contains 126200h this example uses one word of memory and executes in one machine cycle. the pointer is used for memory indirect addressing. the pointer contains the address of the ram (address 00h ). location 00h has operand 1234h . with the accumulator, 005600h , perform an xor instruction to obtain the result 126200h . ([dpsoh xor a, initialization: a contains 3264a0h p21 contains a4h ram bank1: a4h contains 5463h rom address: 5463h contains 1126h instruction: xor a, @@p2:1 result a contains 2342a0h p2:1 contains a41h ram bank1: a4h contains 5464h sr contains 0000h this example uses one word of memory and executes in three machine cycles. the pointer p2:1 contains the ram register location( a4h ). the contents of this register have a rom address. this address refers to the rom data compared to the accumulator. 3264a0h.xor.112600h = 2342a0h . when indirect memory addressing is used, the rom address is automatically incremented. using xor a, @@p2:1+ performs the same operation and also increments the p21 content to a5h . ([dpsoh xor a, initialization: a contains 3264a0h instruction: xor a, #%1126
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& result: a contains 2342a0h sr contains 0000h this example uses two words of memory and executes in two machine cycles. perform an xor instruction on the immediate data. ([dpsoh xor a, initialization: a contains 3264a0h sr contains 0000h bus contains 1126h instruction: xor a, bus result: a contains 2342a0h sr contains this example uses one word of memory and executes in one machine cycle. with the accumulator, perform an xor instruction on the < hwreg > operand. ([dpsoh xor a, initialization: accumulator contains 3264a0h ram bank0: f3h contains 1126h instruction: xor a, %f3 result: a contains 2342a0h sr contains 0000h this example uses one word of memory and executes in one machine cycle. register f3h is compared to the accumulator. 3264a0h.xor.112600h = 2342a0h. an equivalent instruction is xor a, 243 ( f3h = 243 decimal).
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& (ohfwulfdo&kdudfwhulvwlfv 7deoh $evroxwh0d[lpxpdqg0lqlpxp5dwlqjv 6\p 3dudphwhu 0lq 0d[ 8qlwv &rqglwlrqv 9 && 3rzhuvxsso\yrowdjh 9 9 ,' ,qsxwyrowdjh 9 && 9 'ljlwdolqsxwv 9 ,$ ,qsxwyrowdjh 9 && 9 $qdorjlqsxwv$'$' 9 2 2xwsxwyrowdjh 9 && 9 $oosxvksxoogljlwdorxwsxwv 9 2 2xwsxwyrowdjh 9 && 9 3:0rxwsxwv , 2+ 2xwsxwfxuuhqwkljk p$ rqhslq , 2+ 2xwsxwfxuuhqwkljk p$ dooslqv , 2/ 2xwsxwfxuuhqworz p$ rqhslq , 2/ 2xwsxwfxuuhqworz p$ dooslqv 7 $ 2shudwlqjwhpshudwxuh r & 7 6 6wrudjhwhpshudwxuh r & 7deoh '&&kdudfwhulvwlfv 6\pero 3dudphwhu 0lq 7\s 0d[ 8qlwv &rqglwlrqv 9 && 3rzhuvxsso\yrowdjh 9 9 ,/ ,qsxwyrowdjhorz 9 && 9 9 ,+ ,qsxwyrowdjhkljk 9 && 9 && 9 9 ,+5 ,qsxwyrowdjh+ljkrq 5hvhwslq 9 && 9 && 9 9 38 0d[lpxpsxooxs yrowdjh 9 && 9 )ru3:0 9 2/ 2xwsxwyrowdjhorz 9 #, 2/ p$ 9 2+ 2xwsxwyrowdjhkljk 9 && 9 #, 2+ p$ , 2/ 2xwsxwfxuuhqworz p$ #9 2/ y , 2/ 2xwsxwfxuuhqworz p$ #9 2/ y , 2+ 2xwsxwfxuuhqwkljk p$ #9 2+ 9 &&
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& '&3hulskhudov , 2+ 2xwsxwfxuuhqwkljk p$ #9 2+ y , 2/ 2xwsxwfxuuhqw/rz p$ #9 2/ y , 2/ 2xwsxwfxuuhqw/rz p$ #9 2/ y , 2+ 2xwsxwfxuuhqw+ljk p$ #9 2+ 9 && , 2+ 2xwsxwfxuuhqw+ljk p$ #9 2+ 9 9 ;/ ,qsxwyrowdjh;7$/ orz 9 && 9 ([whuqdoforfnjhqhudwru gulyhq 9 ;+ ,qsxwyrowdjh;7$/ kljk 9 && 9 , ,5 5hvhwlqsxwfxuuhqw m $9 5/ 9 , ,/ ,qsxwohdndjh m $ #9dqg9 && , && 6xsso\fxuuhqw p$ $oosruwvduhlqsxwv5*%lvlq gljlwdoprgh , && 6xsso\fxuuhqw p$ $oosruwvduhlqsxwv5*%lvlq dqdorjprgh , && 6xsso\fxuuhqw p$ 6ohhsprgh#n+] , && 6xsso\fxuuhqw m $ 6wrsprghdoo3:0rxwsxwv duh#9 ,1 9 7deoh 99dqg95*%$qdorj2xwsxw 2xwsxw9rowdjh. w /rdg 6hwwolqj7lph #9 && 9 #9 && 9 #9 && 9 ri'&/hyhos) /rdg gdwd 99 99 99 qv gdwd 99 99 99 gdwd 99 99 99 gdwd 99 99 99 7deoh '&&kdudfwhulvwlfv &rqwlqxhg 6\pero 3dudphwhu 0lq 7\s 0d[ 8qlwv &rqglwlrqv
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh $'&6pdoo5dqjh 6\p 3dudphwhu 0lq 7\s 0d[ 8qlwv 8 5 &odpslqjyrowdjhdw $'& 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ,qsxwyrowdjhiruohyho 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& $ ,qsxwyrowdjhiruohyho$ 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& % ,qsxwyrowdjhiruohyho% 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& & ,qsxwyrowdjhiruohyho& 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ' ,qsxwyrowdjhiruohyho' 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ( ,qsxwyrowdjhiruohyho( 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 9 $'& ) ,qsxwyrowdjhiruohyho) 8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5 ,1 ,qsxwlpshgdqfh 0 w 0qvg 86#%vq%8%%8vq8 6jg+prwvxqnvcigngxgnkpfkecvgfkpvjgvcdngkucuykvejrqkpvhtqoqpg#&%ngxgnvqcpqvjgt6qdgkpvjg okffngqhvjgngxgnjcnh.5$
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=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $&&kdudfwhulvwlfv table 81 lists the ac characteristics. 7deoh $'&$'&)xoo5dqjh 'dwd iurp $'& ,qsxw yrowdjh yrowv 'dwd iurp $'& ,qsxw yrowdjh yrowv 'dwd iurp $'& ,qsxw yrowdjh yrowv 'dwd iurp $'& ,qsxw yrowdjh yrowv ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ,qsxwlpshgdqfh !0 w 0qvg 88ee86gor % 7deoh $&&kdudfwhulvwlfv 6\p 3dudphwhu 0lq 7\s 0d[ 8qlwv 7 3& ,qsxwforfnshulrg m 6 7 5& 7 )& &orfnlqsxw5lvhdqg)doo qv 7' 325 3rzhurquhvhwghod\ 6 7: 5(6 3rzhurquhvhwplqlpxpzlgwk 73& m 6 7' +6 +6<1&lqfrplqjvljqdozlgwk m 6 7' 96 96<1&lqfrplqjvljqdozlgwk m 6 7' (6 7lphghod\ehwzhhqohdglqjhgjhri 96<1&dqg+6<1&lq(9(1ilhog m 6 7' 26 7lphghod\ehwzhhqohdglqjhgjhri 96<1&dqg+6<1&lq2''ilhog m 6 7: +96 +6<1&96<1&hgjhzlgwk m 6 0qvg6 # u%vqu%8 %% 8vq8( 15% *\ #nnvkokpiqhvjg+ %dwukpvgthcegctgfghkpgfd[tgncvgfurgekhkecvkqpuqhvjg+ %dwukpvgthceg
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& $1$/2*5*% the rgb outputs in analog mode are controlled current sources with an internal load. these outputs display gamma-corrected, v cc prorated characteristics. see table 82, table 83, and figure 28. )ljxuh 5hfrpphqghg$ssolfdwlrq6fkhpdwlfv 7deoh 5*%9rowdjh6shflilfdwlrq 3dudphwhu 0lq 7\slfdo 0d[ 8qlwv 6xsso\yrowdjh 9 )xoovfdohyrowdjh 9 9 9 && 9 9 vfdohyrowdjh 9 9 9 && 9 9 vfdohyrowdjh 9 9 9 && 9 9 =hurvfdohyrowdjh 2 9 9 && 9 9 0qvg/gcuwtgfykvjm w nqcf 7deoh 5*%7lph6shflilfdwlrq 3dudphwhu 0lq 7\slfdo 0d[ 8qlwv 2xwsxwulvhwlph qv 2xwsxwidoowlph qv 0qvg/gcuwtgfykvjm w tgukuvqtkprctcnngnykvjr(ecrcekvqtnqcf 5 5 5*% 55 . 9 287 5
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 6\vwhp'hvljq&rqvlghudwlrqv the z90356 provides the ability to ? decode closed-caption transmissions ? display characters on the screen ? manipulate analog and digital control circuits ? monitor keypad and infrared signals directly ? generate osd if the z90356 receives vertical and horizontal synchronization signals in a typical system, normal transmission is received and demodulated. the signals received from the color decoder and deflection unit control the crt display. to display characters generated by the z90356 requires a video multiplexor which enables the crt displays rgb signals and synchronization to be controlled by the video outputs from the processor. when the controller has to display a character on the screen, the multiplexor is switched, and the processors video signals appear on the display. the band-limited, a/c-coupled composite video signal is clamped internally to the negative reference voltage (refC) during the back porch interval. it is then passed to the analog-to-digital converter through a 6:1 multiplexor. the digital signal is then decoded to extract the closed-caption text embedded in the video signal. the characters received are generated as video signals and are then passed to the display. when a detectable composite video signal is received, the sync separator extracts the horizontal and vertical synchronization signals and passes them to the deflection module of the television. the flyback signals from the deflection coils are fed back to the z90356. the controller uses these signals to align its video signals with those of the normal display. if the composite video signal is not present, video synchronization is provided by the controller. in this case, the sync signal pins are set to be outputs. the pins then feed to the deflection unit which controls the display. the sync generators can be configured to provide either hsync and vsync, or h-flyback and v-flyback. analog functions such as volume and color controls can be controlled by pulse width modulated outputs from the z90356. additional digital controls like channel fine tuning are controlled via the serial i 2 c bus. an infrared remote control receiver can be directly decoded through the capture register, and keypad input can be scanned by directly controlling i/o pins as keyscan ports. the processor clock is available by referencing an internal phase locked loop to an external 32.768 khz crystal oscillator. the oscillator minimizes emi emissions from the clock circuitry. the internal system clock frequency can be selected as 12.058 mhz in normal operation or 32.768 khz in low power consumption sleep mode (usually used if
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& there is a general system power failure). the z90356s stop mode suspends processor clocking for a power-down. program, display, and character graphics memory are on the chip, eliminating the requirement for external memory components. characters can be displayed as two or three times normal size. smoothing and fringing circuits enhance display appearance. figure 29 diagrams a typical application of the z90356 television controller as an embedded controller in a television. )ljxuh 6\vwhp%orfn'ldjudp 3dfndjlqj figure 30 and table 84 indicate the controlling dimensions. &roru 'hfrghu 'hiohfwlrq 8qlw 5*% 26' 08; 5*% &57 =7hohylvlrq&rqwuroohu ,5 'hwhfwru 7hohylvlrq 7xqhu,) , &%xv &rpsrvlwh 9lghr 7xqlqj &rqwuro )0$xglr 6<1& )o\edfn 9%odqn + 9'hiohfwlrq 6<1& )o\edfn $xglr / 5 &rqwuro 5*% rxwsxw vwdjhv )urqw3dqho &rqwuro
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& )ljxuh 3lq6',33dfndjh'lphqvlrqv d 26 1 27 52 e1 c e ea controlling dimension in inches q1 a2 a1 l b1 b e s detail a optional end lead config detail a
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& 7deoh&rqwuroolqj'lphqvlrqv 6\pero 0loolphwhu 0lq0d[ ,qfk 0lq0d[ $ 2 2 $ % % & ' 2 2 ( ( 7<3 7<3 h$ / 4 6 h
=520dqg=273 .:rug7hohylvlrq&rqwuroohuzlwk26' 3679& &xvwrphu)hhgedfn)rup =3urgxfw6shflilfdwlrq i f there are any problems while operating this product, or any inaccuracies in the specification, please copy and complete this form, then mail or fax it to zilog. suggestions welcome! &xvwrphu,qirupdwlrq 3urgxfw,qirupdwlrq 5hwxuq,qirupdwlrq zilog system test/customer support 910 e. hamilton avenue, suite 110, ms 4C3 campbell, ca 95008 fax: (408) 558-8536 email: tools@zilog.com 3ureohp'hvfulswlrqru6xjjhvwlrq provide a complete description of the problem or suggestion. for specific problems, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. 1dph &rxqwu\ &rpsdq\ 3krqh $gguhvv )d[ &lw\6wdwh=ls (0dlo 6huldoru%rdug)de5hy 6riwzduh9huvlrq 'rfxphqw1xpehu +rvw&rpsxwhu'hvfulswlrq7\sh

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